Lines Matching +full:tx +full:- +full:internal +full:- +full:delay +full:- +full:ps
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
21 - renesas,etheravb-r8a77470 # RZ/G1C
22 - renesas,etheravb-r8a7790 # R-Car H2
23 - renesas,etheravb-r8a7791 # R-Car M2-W
24 - renesas,etheravb-r8a7792 # R-Car V2H
25 - renesas,etheravb-r8a7793 # R-Car M2-N
26 - renesas,etheravb-r8a7794 # R-Car E2
27 - const: renesas,etheravb-rcar-gen2 # R-Car Gen2 and RZ/G1
29 - items:
30 - enum:
31 - renesas,etheravb-r8a774a1 # RZ/G2M
32 - renesas,etheravb-r8a774b1 # RZ/G2N
33 - renesas,etheravb-r8a774c0 # RZ/G2E
34 - renesas,etheravb-r8a774e1 # RZ/G2H
35 - renesas,etheravb-r8a7795 # R-Car H3
36 - renesas,etheravb-r8a7796 # R-Car M3-W
37 - renesas,etheravb-r8a77961 # R-Car M3-W+
38 - renesas,etheravb-r8a77965 # R-Car M3-N
39 - renesas,etheravb-r8a77970 # R-Car V3M
40 - renesas,etheravb-r8a77980 # R-Car V3H
41 - renesas,etheravb-r8a77990 # R-Car E3
42 - renesas,etheravb-r8a77995 # R-Car D3
43 - renesas,etheravb-r8a779a0 # R-Car V3U
44 - const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
46 - items:
47 - enum:
48 - renesas,r9a07g044-gbeth # RZ/G2{L,LC}
49 - const: renesas,rzg2l-gbeth # RZ/G2L
55 interrupt-names: true
59 clock-names: true
64 power-domains:
70 phy-mode: true
72 phy-handle: true
74 '#address-cells':
78 '#size-cells':
82 renesas,no-ether-link:
87 renesas,ether-link-active-low:
90 Specify when the AVB_LINK signal is active-low instead of normal
91 active-high.
93 rx-internal-delay-ps:
96 tx-internal-delay-ps:
100 "^ethernet-phy@[0-9a-f]$":
102 $ref: ethernet-phy.yaml#
105 - compatible
106 - reg
107 - interrupts
108 - clocks
109 - power-domains
110 - resets
111 - phy-mode
112 - phy-handle
113 - '#address-cells'
114 - '#size-cells'
117 - $ref: ethernet-controller.yaml#
119 - if:
124 - renesas,etheravb-rcar-gen2
125 - renesas,etheravb-r8a7795
126 - renesas,etheravb-r8a7796
127 - renesas,etheravb-r8a77961
128 - renesas,etheravb-r8a77965
133 - description: MAC register block
134 - description: Stream buffer
139 - description: MAC register block
141 - if:
146 - renesas,etheravb-rcar-gen2
147 - renesas,rzg2l-gbeth
153 interrupt-names:
156 - const: mux
157 - const: fil
158 - const: arp_ns
159 rx-internal-delay-ps: false
165 interrupt-names:
167 pattern: '^ch[0-9]+$'
169 - interrupt-names
170 - rx-internal-delay-ps
172 - if:
177 - renesas,etheravb-r8a774a1
178 - renesas,etheravb-r8a774b1
179 - renesas,etheravb-r8a774e1
180 - renesas,etheravb-r8a7795
181 - renesas,etheravb-r8a7796
182 - renesas,etheravb-r8a77961
183 - renesas,etheravb-r8a77965
184 - renesas,etheravb-r8a77970
185 - renesas,etheravb-r8a77980
186 - renesas,etheravb-r8a779a0
189 - tx-internal-delay-ps
192 tx-internal-delay-ps: false
194 - if:
198 const: renesas,etheravb-r8a77995
201 rx-internal-delay-ps:
204 - if:
208 const: renesas,etheravb-r8a77980
211 tx-internal-delay-ps:
214 - if:
218 const: renesas,rzg2l-gbeth
223 - description: Main clock
224 - description: Register access clock
225 - description: Reference clock for RGMII
226 clock-names:
228 - const: axi
229 - const: chi
230 - const: refclk
236 - description: AVB functional clock
237 - description: Optional TXC reference clock
238 clock-names:
241 - const: fck
242 - const: refclk
247 - |
248 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
249 #include <dt-bindings/interrupt-controller/arm-gic.h>
250 #include <dt-bindings/power/r8a7795-sysc.h>
251 #include <dt-bindings/gpio/gpio.h>
257 compatible = "renesas,etheravb-r8a7795",
258 "renesas,etheravb-rcar-gen3";
285 interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6",
291 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
293 phy-mode = "rgmii";
294 phy-handle = <&phy0>;
295 rx-internal-delay-ps = <0>;
296 tx-internal-delay-ps = <2000>;
297 #address-cells = <1>;
298 #size-cells = <0>;
300 phy0: ethernet-phy@0 {
301 rxc-skew-ps = <1500>;
303 interrupt-parent = <&gpio2>;
305 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;