| /Linux-v6.1/drivers/net/ethernet/google/gve/ |
| D | gve_tx.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2021 Google, Inc.
19 iowrite32be(val, &priv->db_bar2[be32_to_cpu(q_resources->db_index)]); in gve_tx_put_doorbell()
23 * We copy skb payloads into the registered segment before writing Tx
24 * descriptors and ringing the Tx doorbell.
26 * gve_tx_fifo_* manages the Registered Segment as a FIFO - clients must
30 static int gve_tx_fifo_init(struct gve_priv *priv, struct gve_tx_fifo *fifo) in gve_tx_fifo_init() argument
32 fifo->base = vmap(fifo->qpl->pages, fifo->qpl->num_entries, VM_MAP, in gve_tx_fifo_init()
34 if (unlikely(!fifo->base)) { in gve_tx_fifo_init()
35 netif_err(priv, drv, priv->dev, "Failed to vmap fifo, qpl_id = %d\n", in gve_tx_fifo_init()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | ibm,emac.txt | 8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
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| D | altr,tse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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| /Linux-v6.1/drivers/platform/mellanox/ |
| D | mlxbf-tmfifo.c | 1 // SPDX-License-Identifier: GPL-2.0+
24 #include "mlxbf-tmfifo-regs.h"
26 /* Vring size. */
29 /* Console Tx buffer size. */
32 /* Console Tx buffer reserved space. */
35 /* House-keeping timer interval. */
38 /* Virtual devices sharing the TM FIFO. */
53 * mlxbf_tmfifo_vring - Structure of the TmFifo virtual ring
63 * @num: vring size (number of descriptors)
64 * @align: vring alignment size
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| /Linux-v6.1/arch/powerpc/boot/dts/ |
| D | mpc5121.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2007-2008 Freescale Semiconductor Inc.
8 #include <dt-bindings/clock/mpc512x-clock.h>
10 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&ipic>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; /* 32 bytes */
[all …]
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| D | eiger.dts | 11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
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| D | arches.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpc5121-psc.txt | 4 ----------------
7 are specified by fsl,mpc5121-psc-uart nodes in the
8 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
9 Controller node fsl,mpc5121-psc-fifo is required there:
11 fsl,mpc512x-psc-uart nodes
12 --------------------------
15 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
17 - reg : Offset and length of the register set for the PSC device
18 - interrupts : <a b> where a is the interrupt number of the
19 PSC FIFO Controller and b is a field that represents an
[all …]
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| /Linux-v6.1/drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_mbx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
7 * fm10k_fifo_init - Initialize a message FIFO
8 * @fifo: pointer to FIFO
9 * @buffer: pointer to memory to be used to store FIFO
10 * @size: maximum message size to store in FIFO, must be 2^n - 1
12 static void fm10k_fifo_init(struct fm10k_mbx_fifo *fifo, u32 *buffer, u16 size) in fm10k_fifo_init() argument
14 fifo->buffer = buffer; in fm10k_fifo_init()
15 fifo->size = size; in fm10k_fifo_init()
16 fifo->head = 0; in fm10k_fifo_init()
[all …]
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| /Linux-v6.1/drivers/net/ethernet/sun/ |
| D | sunqe.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define GLOB_PSIZE 0x08UL /* Packet Size */
15 #define GLOB_MSIZE 0x0cUL /* Local-memory Size */
16 #define GLOB_RSIZE 0x10UL /* Receive partition size */
17 #define GLOB_TSIZE 0x14UL /* Transmit partition size */
34 #define GLOB_PSIZE_2048 0x00 /* 2k packet size */
35 #define GLOB_PSIZE_4096 0x01 /* 4k packet size */
36 #define GLOB_PSIZE_6144 0x10 /* 6k packet size */
37 #define GLOB_PSIZE_8192 0x11 /* 8k packet size */
45 /* The following registers are for per-qe channel information/status. */
[all …]
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| D | sungem.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 #define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */
39 * This auto-clearing does not occur when the alias at GREG_STAT2
45 #define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */
46 #define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */
47 #define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */
52 #define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */
69 * signalled to the cpu. GREG_IACK can be used to clear specific top-level
96 * This register is used to perform a global reset of the RX and TX portions
97 * of the GEM asic. Setting the RX or TX reset bit will start the reset.
[all …]
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| D | cassini.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
45 * DEFAULT: 0x0, SIZE: 5 bits
54 /* if enabled, BIM can send bursts across PCI bus > cacheline size. burst
57 * DEFAULT: 0x0, SIZE: 1 bit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
[all …]
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| /Linux-v6.1/arch/m68k/include/asm/ |
| D | m54xxpci.h | 4 * m54xxpci.h -- ColdFire 547x and 548x PCI bus support
45 #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
46 #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
47 #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
48 #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
49 #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
50 #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
51 #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
52 #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
53 #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
[all …]
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| /Linux-v6.1/drivers/net/can/spi/mcp251xfd/ |
| D | mcp251xfd-ram.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
9 #include "mcp251xfd-ram.h"
17 max = min_t(u8, obj->max, obj->fifo_num * config->fifo_depth); in can_ram_clamp()
18 return clamp(val, obj->min, max); in can_ram_clamp()
26 u8 fifo_num = obj->fifo_num; in can_ram_rounddown_pow_of_two()
32 /* Use 1st FIFO for coalescing, if requested. in can_ram_rounddown_pow_of_two()
34 * Either use complete FIFO (and FIFO Full IRQ) for in can_ram_rounddown_pow_of_two()
35 * coalescing or only half of FIFO (FIFO Half Full in can_ram_rounddown_pow_of_two()
[all …]
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| D | mcp251xfd-ring.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
6 // Marc Kleine-Budde <kernel@pengutronix.de>
18 #include "mcp251xfd-ram.h"
31 len = last_byte - first_byte + 1; in mcp251xfd_cmd_prepare_write_reg()
37 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) { in mcp251xfd_cmd_prepare_write_reg()
40 mcp251xfd_spi_cmd_crc_set_len_in_reg(&write_reg_buf->crc.cmd, in mcp251xfd_cmd_prepare_write_reg()
43 len += sizeof(write_reg_buf->crc.cmd); in mcp251xfd_cmd_prepare_write_reg()
44 crc = mcp251xfd_crc16_compute(&write_reg_buf->crc, len); in mcp251xfd_cmd_prepare_write_reg()
48 len += sizeof(write_reg_buf->crc.crc); in mcp251xfd_cmd_prepare_write_reg()
[all …]
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| /Linux-v6.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | ampdu.c | 31 /* max Tx ba window size (in pdu) */
33 /* default Tx ba window size (in pdu) */
35 /* default Rx ba window size (in pdu) */
37 /* max Rx ba window size (in pdu) */
39 /* max dur of tx ampdu (in msec) */
41 /* default tx retry limit */
43 /* default tx retry limit at reg rate */
52 #define NUM_FFPLD_FIFO 4 /* number of fifo concerned by pre-loading */
56 #define FFPLD_MPDU_SIZE 1800 /* estimate of maximum mpdu size */
76 #define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
[all …]
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| /Linux-v6.1/drivers/spi/ |
| D | spi-zynq-qspi.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #include <linux/spi/spi-mem.h>
28 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst, WO */
29 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst, WO */
30 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst, WO */
31 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst, WO */
34 #define ZYNQ_QSPI_TX_THRESH_OFFSET 0x28 /* TX FIFO Watermark Reg, RW */
35 #define ZYNQ_QSPI_RX_THRESH_OFFSET 0x2C /* RX FIFO Watermark Reg, RW */
47 #define ZYNQ_QSPI_CONFIG_MANSRT_MASK BIT(16) /* Manual TX Start */
48 #define ZYNQ_QSPI_CONFIG_MANSRTEN_MASK BIT(15) /* Enable Manual TX Mode */
[all …]
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| D | spi-mpc512x-psc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Hongjun Chen <hong-jun.chen@freescale.com>
39 switch (mps->type) { \
41 struct mpc52xx_psc __iomem *psc = mps->psc; \
42 __ret = &psc->regname; \
46 struct mpc5125_psc __iomem *psc = mps->psc; \
47 __ret = &psc->regname; \
59 struct mpc512x_psc_fifo __iomem *fifo; member
81 struct mpc512x_psc_spi_cs *cs = spi->controller_state; in mpc512x_psc_spi_transfer_setup()
83 cs->speed_hz = (t && t->speed_hz) in mpc512x_psc_spi_transfer_setup()
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | sama5d2.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
9 #include <dt-bindings/dma/at91.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/at91.h>
12 #include <dt-bindings/mfd/at91-usart.h>
13 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 interrupt-parent = <&aic>;
[all …]
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| D | lan966x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
[all …]
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| D | bcm283x-rpi-usb-otg.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
4 g-rx-fifo-size = <256>;
5 g-np-tx-fifo-size = <32>;
8 * fifo sizes shouldn't exceed 3776 bytes.
10 g-tx-fifo-size = <256 256 512 512 512 768 768>;
|
| /Linux-v6.1/drivers/net/ethernet/tehuti/ |
| D | tehuti.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * 1) RX Free Fifo - RXF - holds descriptors of empty buffers to accept incoming
13 * traffic. This Fifo is filled by SW and is readen by HW. Each descriptor holds
14 * info about buffer's location, size and ID. An ID field is used to identify a
15 * buffer when it's returned with data via RXD Fifo (see below)
16 * 2) RX Data Fifo - RXD - holds descriptors of full buffers. This Fifo is
18 * HW pops descriptor from RXF Fifo, stores ID, fills buffer with incoming data,
20 * pushes it into RXD Fifo and raises interrupt to indicate new RX data.
23 * One holds 1.5K packets and another - 26K packets. Depending on incoming
24 * packet size, HW desides on a RXF Fifo to pop buffer from. When packet is
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
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| /Linux-v6.1/drivers/rpmsg/ |
| D | qcom_glink_rpm.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2017, Linaro Ltd
26 #define RPM_TOC_MAX_ENTRIES ((RPM_TOC_SIZE - sizeof(struct rpm_toc)) / \
37 __le32 size; member
53 void __iomem *fifo; member
62 head = readl(pipe->head); in glink_rpm_rx_avail()
63 tail = readl(pipe->tail); in glink_rpm_rx_avail()
66 return pipe->native.length - tail + head; in glink_rpm_rx_avail()
68 return head - tail; in glink_rpm_rx_avail()
78 tail = readl(pipe->tail); in glink_rpm_rx_peak()
[all …]
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