/Linux-v6.1/Documentation/devicetree/bindings/display/tegra/ |
D | nvidia,tegra186-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-display.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra186 (and later) Display Hub 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^display-hub@[0-9a-f]+$" 19 - nvidia,tegra186-display 20 - nvidia,tegra194-display [all …]
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D | nvidia,tegra186-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra186 (and later) Display Controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^display@[0-9a-f]+$" 19 - nvidia,tegra186-dc 20 - nvidia,tegra194-dc [all …]
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D | nvidia,tegra124-sor.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-sor.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 19 pattern: "^sor@[0-9a-f]+$" 23 - enum: 24 - nvidia,tegra124-sor 25 - nvidia,tegra210-sor [all …]
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D | nvidia,tegra124-dpaux.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 14 The Tegra Display Port Auxiliary (DPAUX) pad controller manages two 24 pattern: "^dpaux@[0-9a-f]+$" 28 - enum: 29 - nvidia,tegra124-dpaux [all …]
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D | nvidia,tegra124-vic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-vic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^vic@[0-9a-f]+$" 19 - enum: 20 - nvidia,tegra124-vic 21 - nvidia,tegra210-vic [all …]
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D | nvidia,tegra20-vi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^vi@[0-9a-f]+$" 19 - const: nvidia,tegra20-vi 20 - const: nvidia,tegra30-vi 21 - const: nvidia,tegra114-vi [all …]
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D | nvidia,tegra20-host1x.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 13 description: The host1x top-level node defines a number of children, each 19 - enum: 20 - nvidia,tegra20-host1x 21 - nvidia,tegra30-host1x [all …]
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/Linux-v6.1/arch/arm64/boot/dts/nvidia/ |
D | tegra194.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/tegra194-clock.h> 3 #include <dt-bindings/gpio/tegra194-gpio.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mailbox/tegra186-hsp.h> 6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7 #include <dt-bindings/pinctrl/pinctrl-tegra.h> 8 #include <dt-bindings/power/tegra194-powergate.h> 9 #include <dt-bindings/reset/tegra194-reset.h> 10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h> [all …]
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D | tegra194-p2972-0000.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/linux-event-codes.h> 5 #include <dt-bindings/input/gpio-keys.h> 7 #include "tegra194-p2888.dtsi" 11 compatible = "nvidia,p2972-0000", "nvidia,tegra194"; 17 dma-controller@2930000 { 21 interrupt-controller@2a40000 { 29 #address-cells = <1>; 30 #size-cells = <0>; [all …]
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/Linux-v6.1/drivers/iommu/arm/arm-smmu/ |
D | arm-smmu-nvidia.c | 1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved. 12 #include "arm-smmu.h" 15 * Tegra194 has three ARM MMU-500 Instances. 18 * non-isochronous HW devices. 23 * memory client. This is necessary to allow for use-case such as seamlessly 24 * handing over the display controller configuration from the firmware to the 52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page() 69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg() 90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64() [all …]
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/Linux-v6.1/sound/pci/hda/ |
D | hda_tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include <linux/dma-mapping.h> 66 * Tegra194 does not reflect correct number of SDO lines. Below macro 92 "Automatic power-saving timeout (in seconds, 0 = disable)."); 104 v = readl(hda->regs + HDA_IPFS_CONFIG); in hda_tegra_init() 106 writel(v, hda->regs + HDA_IPFS_CONFIG); in hda_tegra_init() 109 v = readl(hda->regs + HDA_CFG_CMD); in hda_tegra_init() 113 writel(v, hda->regs + HDA_CFG_CMD); in hda_tegra_init() 115 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0); in hda_tegra_init() 116 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0); in hda_tegra_init() [all …]
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D | patch_hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 89 bool chmap_set; /* channel-map override by ALSA API? */ 90 unsigned char chmap[8]; /* ALSA API channel-map */ 126 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 174 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 176 * Non-generic VIA/NVIDIA specific [all …]
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/Linux-v6.1/drivers/gpu/drm/tegra/ |
D | hub.c | 1 // SPDX-License-Identifier: GPL-2.0-only 8 #include <linux/dma-mapping.h> 64 * The GPU sector layout is only supported on Tegra194, but these will 65 * be filtered out later on by ->format_mod_supported() on SoCs where 82 offset = 0x000 + (offset - 0x500); in tegra_plane_offset() 83 return plane->offset + offset; in tegra_plane_offset() 87 offset = 0x180 + (offset - 0x700); in tegra_plane_offset() 88 return plane->offset + offset; in tegra_plane_offset() 92 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset() 93 return plane->offset + offset; in tegra_plane_offset() [all …]
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D | drm.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. 27 #include <asm/dma-iommu.h> 79 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail() 80 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail() 82 if (tegra->hub) { in tegra_atomic_commit_tail() 111 return -ENOMEM; in tegra_drm_open() 113 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open() 114 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open() 115 xa_init(&fpriv->syncpoints); in tegra_drm_open() [all …]
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D | dpaux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/pinctrl/pinconf-generic.h> 21 #include <drm/display/drm_dp_helper.h> 22 #include <drm/display/drm_dp_aux_bus.h> 79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl() 81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl() 89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel() 90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel() 99 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_write_fifo() 115 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_read_fifo() [all …]
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D | dc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/dma-mapping.h> 42 stats->frames = 0; in tegra_dc_stats_reset() 43 stats->vblank = 0; in tegra_dc_stats_reset() 44 stats->underflow = 0; in tegra_dc_stats_reset() 45 stats->overflow = 0; in tegra_dc_stats_reset() 64 offset = 0x000 + (offset - 0x500); in tegra_plane_offset() 65 return plane->offset + offset; in tegra_plane_offset() 69 offset = 0x180 + (offset - 0x700); in tegra_plane_offset() 70 return plane->offset + offset; in tegra_plane_offset() [all …]
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D | sor.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 19 #include <drm/display/drm_dp_helper.h> 20 #include <drm/display/drm_scdc_helper.h> 486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() 488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl() 496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel() 497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel() 504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock() 506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock() [all …]
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/Linux-v6.1/drivers/soc/tegra/ |
D | pmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 14 #include <linux/arm-smccc.h> 16 #include <linux/clk-provider.h> 18 #include <linux/clk/clk-conf.h> 36 #include <linux/pinctrl/pinconf-generic.h> 54 #include <dt-bindings/interrupt-controller/arm-gic.h> 55 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 56 #include <dt-bindings/gpio/tegra186-gpio.h> [all …]
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