Lines Matching +full:tegra194 +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
42 stats->frames = 0; in tegra_dc_stats_reset()
43 stats->vblank = 0; in tegra_dc_stats_reset()
44 stats->underflow = 0; in tegra_dc_stats_reset()
45 stats->overflow = 0; in tegra_dc_stats_reset()
64 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
65 return plane->offset + offset; in tegra_plane_offset()
69 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
70 return plane->offset + offset; in tegra_plane_offset()
74 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
75 return plane->offset + offset; in tegra_plane_offset()
78 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
80 return plane->offset + offset; in tegra_plane_offset()
86 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
92 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
97 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
102 if (it.node == dev->of_node) in tegra_dc_has_output()
109 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
111 * Latching happens mmediately if the display controller is in STOP mode or
114 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
117 * into the ACTIVE copy, either immediately if the display controller is in
151 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()
152 inf.full -= dfixed_const(1); in compute_dda_inc()
180 /* disable blending for non-overlapping case */ in tegra_plane_setup_blending_legacy()
184 state = to_tegra_plane_state(plane->base.state); in tegra_plane_setup_blending_legacy()
186 if (state->opaque) { in tegra_plane_setup_blending_legacy()
188 * Since custom fix-weight blending isn't utilized and weight in tegra_plane_setup_blending_legacy()
205 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
207 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
208 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
230 if (state->blending[i].alpha && in tegra_plane_setup_blending_legacy()
231 state->blending[i].top) in tegra_plane_setup_blending_legacy()
235 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
237 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
238 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
248 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
249 state->blending[0].top) in tegra_plane_setup_blending_legacy()
252 if (state->blending[1].alpha && in tegra_plane_setup_blending_legacy()
253 state->blending[1].top) in tegra_plane_setup_blending_legacy()
259 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
272 if (!state->blending[0].top && state->blending[1].top) { in tegra_plane_setup_blending_legacy()
308 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); in tegra_plane_setup_blending()
316 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering()
318 if (window->src.w == window->dst.w) in tegra_plane_use_horizontal_filtering()
321 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
331 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering()
333 if (window->src.h == window->dst.h) in tegra_plane_use_vertical_filtering()
336 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
339 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
349 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window()
358 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL); in tegra_dc_setup_window()
360 bpp = window->bits_per_pixel / 8; in tegra_dc_setup_window()
364 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
365 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
367 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); in tegra_dc_setup_window()
370 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); in tegra_dc_setup_window()
373 h_offset = window->src.x * bpp; in tegra_dc_setup_window()
374 v_offset = window->src.y; in tegra_dc_setup_window()
375 h_size = window->src.w * bpp; in tegra_dc_setup_window()
376 v_size = window->src.h; in tegra_dc_setup_window()
378 if (window->reflect_x) in tegra_dc_setup_window()
379 h_offset += (window->src.w - 1) * bpp; in tegra_dc_setup_window()
381 if (window->reflect_y) in tegra_dc_setup_window()
382 v_offset += window->src.h - 1; in tegra_dc_setup_window()
394 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); in tegra_dc_setup_window()
395 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); in tegra_dc_setup_window()
400 h_dda = compute_initial_dda(window->src.x); in tegra_dc_setup_window()
401 v_dda = compute_initial_dda(window->src.y); in tegra_dc_setup_window()
409 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
412 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
415 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
417 value = window->stride[1] << 16 | window->stride[0]; in tegra_dc_setup_window()
420 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
426 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
427 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
429 switch (window->tiling.mode) { in tegra_dc_setup_window()
446 switch (window->tiling.mode) { in tegra_dc_setup_window()
459 * No need to handle this here because ->atomic_check in tegra_dc_setup_window()
482 } else if (window->bits_per_pixel < 24) { in tegra_dc_setup_window()
486 if (window->reflect_x) in tegra_dc_setup_window()
489 if (window->reflect_y) in tegra_dc_setup_window()
494 * Enable horizontal 6-tap filter and set filtering in tegra_dc_setup_window()
521 * Enable vertical 2-tap filter and set filtering in tegra_dc_setup_window()
524 for (i = 0, k = 128; i < 16; i++, k -= 8) in tegra_dc_setup_window()
532 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
545 /* non-native formats */
625 unsigned int rotation = new_plane_state->rotation; in tegra_plane_atomic_check()
626 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check()
628 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check()
631 plane_state->peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
632 plane_state->avg_memory_bandwidth = 0; in tegra_plane_atomic_check()
635 if (!new_plane_state->crtc) { in tegra_plane_atomic_check()
636 plane_state->total_peak_memory_bandwidth = 0; in tegra_plane_atomic_check()
640 err = tegra_plane_format(new_plane_state->fb->format->format, in tegra_plane_atomic_check()
641 &plane_state->format, in tegra_plane_atomic_check()
642 &plane_state->swap); in tegra_plane_atomic_check()
652 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
658 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); in tegra_plane_atomic_check()
662 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
663 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
665 return -EINVAL; in tegra_plane_atomic_check()
674 if (tegra_fb_is_bottom_up(new_plane_state->fb)) in tegra_plane_atomic_check()
680 plane_state->reflect_x = true; in tegra_plane_atomic_check()
682 plane_state->reflect_x = false; in tegra_plane_atomic_check()
685 plane_state->reflect_y = true; in tegra_plane_atomic_check()
687 plane_state->reflect_y = false; in tegra_plane_atomic_check()
691 * error out if the user tries to display a framebuffer with such a in tegra_plane_atomic_check()
694 if (new_plane_state->fb->format->num_planes > 2) { in tegra_plane_atomic_check()
695 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { in tegra_plane_atomic_check()
696 DRM_ERROR("unsupported UV-plane configuration\n"); in tegra_plane_atomic_check()
697 return -EINVAL; in tegra_plane_atomic_check()
717 if (!old_state || !old_state->crtc) in tegra_plane_atomic_disable()
731 struct drm_framebuffer *fb = new_state->fb; in tegra_plane_atomic_update()
737 if (!new_state->crtc || !new_state->fb) in tegra_plane_atomic_update()
740 if (!new_state->visible) in tegra_plane_atomic_update()
744 window.src.x = new_state->src.x1 >> 16; in tegra_plane_atomic_update()
745 window.src.y = new_state->src.y1 >> 16; in tegra_plane_atomic_update()
746 window.src.w = drm_rect_width(&new_state->src) >> 16; in tegra_plane_atomic_update()
747 window.src.h = drm_rect_height(&new_state->src) >> 16; in tegra_plane_atomic_update()
748 window.dst.x = new_state->dst.x1; in tegra_plane_atomic_update()
749 window.dst.y = new_state->dst.y1; in tegra_plane_atomic_update()
750 window.dst.w = drm_rect_width(&new_state->dst); in tegra_plane_atomic_update()
751 window.dst.h = drm_rect_height(&new_state->dst); in tegra_plane_atomic_update()
752 window.bits_per_pixel = fb->format->cpp[0] * 8; in tegra_plane_atomic_update()
753 window.reflect_x = tegra_plane_state->reflect_x; in tegra_plane_atomic_update()
754 window.reflect_y = tegra_plane_state->reflect_y; in tegra_plane_atomic_update()
757 window.zpos = new_state->normalized_zpos; in tegra_plane_atomic_update()
758 window.tiling = tegra_plane_state->tiling; in tegra_plane_atomic_update()
759 window.format = tegra_plane_state->format; in tegra_plane_atomic_update()
760 window.swap = tegra_plane_state->swap; in tegra_plane_atomic_update()
762 for (i = 0; i < fb->format->num_planes; i++) { in tegra_plane_atomic_update()
763 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; in tegra_plane_atomic_update()
768 * function, so it's safe to ignore the V-plane pitch here. in tegra_plane_atomic_update()
771 window.stride[i] = fb->pitches[i]; in tegra_plane_atomic_update()
799 return 1 << drm->mode_config.num_crtc; in tegra_plane_get_possible_crtcs()
815 return ERR_PTR(-ENOMEM); in tegra_primary_plane_create()
818 plane->offset = 0xa00; in tegra_primary_plane_create()
819 plane->index = 0; in tegra_primary_plane_create()
820 plane->dc = dc; in tegra_primary_plane_create()
822 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
823 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
824 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
832 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_primary_plane_create()
840 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_primary_plane_create()
841 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_primary_plane_create()
843 err = drm_plane_create_rotation_property(&plane->base, in tegra_primary_plane_create()
850 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
853 return &plane->base; in tegra_primary_plane_create()
873 plane_state->peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
874 plane_state->avg_memory_bandwidth = 0; in tegra_cursor_atomic_check()
877 if (!new_plane_state->crtc) { in tegra_cursor_atomic_check()
878 plane_state->total_peak_memory_bandwidth = 0; in tegra_cursor_atomic_check()
883 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || in tegra_cursor_atomic_check()
884 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) in tegra_cursor_atomic_check()
885 return -EINVAL; in tegra_cursor_atomic_check()
888 if (new_plane_state->src_w != new_plane_state->src_h) in tegra_cursor_atomic_check()
889 return -EINVAL; in tegra_cursor_atomic_check()
891 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && in tegra_cursor_atomic_check()
892 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) in tegra_cursor_atomic_check()
893 return -EINVAL; in tegra_cursor_atomic_check()
906 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in __tegra_cursor_atomic_update()
907 struct tegra_drm *tegra = plane->dev->dev_private; in __tegra_cursor_atomic_update()
909 u64 dma_mask = *dc->dev->dma_mask; in __tegra_cursor_atomic_update()
915 if (!new_state->crtc || !new_state->fb) in __tegra_cursor_atomic_update()
919 * Legacy display supports hardware clipping of the cursor, but in __tegra_cursor_atomic_update()
922 if (!dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
925 switch (new_state->crtc_w) { in __tegra_cursor_atomic_update()
944 new_state->crtc_w, new_state->crtc_h); in __tegra_cursor_atomic_update()
948 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; in __tegra_cursor_atomic_update()
952 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); in __tegra_cursor_atomic_update()
965 if (dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
976 if (dc->soc->has_nvdisplay) { in __tegra_cursor_atomic_update()
979 x = new_state->dst.x1; in __tegra_cursor_atomic_update()
980 y = new_state->dst.y1; in __tegra_cursor_atomic_update()
982 drm_rect_fp_to_int(&src, &new_state->src); in __tegra_cursor_atomic_update()
984 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); in __tegra_cursor_atomic_update()
987 value = (drm_rect_height(&src) & tegra->vmask) << 16 | in __tegra_cursor_atomic_update()
988 (drm_rect_width(&src) & tegra->hmask); in __tegra_cursor_atomic_update()
991 x = new_state->crtc_x; in __tegra_cursor_atomic_update()
992 y = new_state->crtc_y; in __tegra_cursor_atomic_update()
996 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); in __tegra_cursor_atomic_update()
1017 if (!old_state || !old_state->crtc) in tegra_cursor_atomic_disable()
1020 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1034 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc); in tegra_cursor_atomic_async_check()
1036 return -EINVAL; in tegra_cursor_atomic_async_check()
1038 if (!crtc_state->active) in tegra_cursor_atomic_async_check()
1039 return -EINVAL; in tegra_cursor_atomic_async_check()
1041 if (plane->state->crtc != new_state->crtc || in tegra_cursor_atomic_async_check()
1042 plane->state->src_w != new_state->src_w || in tegra_cursor_atomic_async_check()
1043 plane->state->src_h != new_state->src_h || in tegra_cursor_atomic_async_check()
1044 plane->state->crtc_w != new_state->crtc_w || in tegra_cursor_atomic_async_check()
1045 plane->state->crtc_h != new_state->crtc_h || in tegra_cursor_atomic_async_check()
1046 plane->state->fb != new_state->fb || in tegra_cursor_atomic_async_check()
1047 plane->state->fb == NULL) in tegra_cursor_atomic_async_check()
1048 return -EINVAL; in tegra_cursor_atomic_async_check()
1058 if (new_state->visible != plane->state->visible) in tegra_cursor_atomic_async_check()
1059 return -EINVAL; in tegra_cursor_atomic_async_check()
1068 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_async_update()
1070 plane->state->src_x = new_state->src_x; in tegra_cursor_atomic_async_update()
1071 plane->state->src_y = new_state->src_y; in tegra_cursor_atomic_async_update()
1072 plane->state->crtc_x = new_state->crtc_x; in tegra_cursor_atomic_async_update()
1073 plane->state->crtc_y = new_state->crtc_y; in tegra_cursor_atomic_async_update()
1075 if (new_state->visible) { in tegra_cursor_atomic_async_update()
1081 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; in tegra_cursor_atomic_async_update()
1085 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; in tegra_cursor_atomic_async_update()
1117 return ERR_PTR(-ENOMEM); in tegra_dc_cursor_plane_create()
1124 * need to special-casing the cursor plane. in tegra_dc_cursor_plane_create()
1126 plane->index = 6; in tegra_dc_cursor_plane_create()
1127 plane->dc = dc; in tegra_dc_cursor_plane_create()
1129 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1143 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_cursor_plane_create()
1152 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); in tegra_dc_cursor_plane_create()
1153 drm_plane_create_zpos_immutable_property(&plane->base, 255); in tegra_dc_cursor_plane_create()
1155 return &plane->base; in tegra_dc_cursor_plane_create()
1165 /* non-native formats */
1202 /* semi-planar formats */
1242 /* semi-planar formats */
1265 return ERR_PTR(-ENOMEM); in tegra_dc_overlay_plane_create()
1267 plane->offset = 0xa00 + 0x200 * index; in tegra_dc_overlay_plane_create()
1268 plane->index = index; in tegra_dc_overlay_plane_create()
1269 plane->dc = dc; in tegra_dc_overlay_plane_create()
1271 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1272 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1285 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_overlay_plane_create()
1294 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_dc_overlay_plane_create()
1295 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_dc_overlay_plane_create()
1297 err = drm_plane_create_rotation_property(&plane->base, in tegra_dc_overlay_plane_create()
1304 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1307 return &plane->base; in tegra_dc_overlay_plane_create()
1316 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1317 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1319 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1320 for (j = 0; j < wgrp->num_windows; j++) { in tegra_dc_add_shared_planes()
1321 unsigned int index = wgrp->windows[j]; in tegra_dc_add_shared_planes()
1324 wgrp->index, in tegra_dc_add_shared_planes()
1334 plane->type = DRM_PLANE_TYPE_PRIMARY; in tegra_dc_add_shared_planes()
1356 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1367 while (i--) in tegra_dc_add_planes()
1368 planes[i]->funcs->destroy(planes[i]); in tegra_dc_add_planes()
1370 primary->funcs->destroy(primary); in tegra_dc_add_planes()
1387 if (crtc->state) in tegra_crtc_reset()
1388 tegra_crtc_atomic_destroy_state(crtc, crtc->state); in tegra_crtc_reset()
1390 __drm_atomic_helper_crtc_reset(crtc, &state->base); in tegra_crtc_reset()
1396 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_duplicate_state()
1403 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); in tegra_crtc_atomic_duplicate_state()
1404 copy->clk = state->clk; in tegra_crtc_atomic_duplicate_state()
1405 copy->pclk = state->pclk; in tegra_crtc_atomic_duplicate_state()
1406 copy->div = state->div; in tegra_crtc_atomic_duplicate_state()
1407 copy->planes = state->planes; in tegra_crtc_atomic_duplicate_state()
1409 return ©->base; in tegra_crtc_atomic_duplicate_state()
1638 struct drm_info_node *node = s->private; in tegra_dc_show_regs()
1639 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs()
1643 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1645 if (!dc->base.state->active) { in tegra_dc_show_regs()
1646 err = -EBUSY; in tegra_dc_show_regs()
1653 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, in tegra_dc_show_regs()
1658 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1664 struct drm_info_node *node = s->private; in tegra_dc_show_crc()
1665 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc()
1669 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1671 if (!dc->base.state->active) { in tegra_dc_show_crc()
1672 err = -EBUSY; in tegra_dc_show_crc()
1680 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1681 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1689 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1695 struct drm_info_node *node = s->private; in tegra_dc_show_stats()
1696 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats()
1698 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1699 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1700 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1701 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1703 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1704 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1705 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1706 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1720 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_late_register()
1725 root = crtc->debugfs_entry; in tegra_dc_late_register()
1730 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1732 if (!dc->debugfs_files) in tegra_dc_late_register()
1733 return -ENOMEM; in tegra_dc_late_register()
1736 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1738 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1746 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_early_unregister()
1749 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1750 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1751 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1759 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1760 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1763 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1809 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1816 value = ((mode->vsync_end - mode->vsync_start) << 16) | in tegra_dc_set_timings()
1817 ((mode->hsync_end - mode->hsync_start) << 0); in tegra_dc_set_timings()
1820 value = ((mode->vtotal - mode->vsync_end) << 16) | in tegra_dc_set_timings()
1821 ((mode->htotal - mode->hsync_end) << 0); in tegra_dc_set_timings()
1824 value = ((mode->vsync_start - mode->vdisplay) << 16) | in tegra_dc_set_timings()
1825 ((mode->hsync_start - mode->hdisplay) << 0); in tegra_dc_set_timings()
1828 value = (mode->vdisplay << 16) | mode->hdisplay; in tegra_dc_set_timings()
1835 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1837 * @dc: display controller
1839 * @clk: parent clock for display controller
1844 * 0 on success or a negative error-code on failure.
1853 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1854 return -EINVAL; in tegra_dc_state_setup_clock()
1856 state->clk = clk; in tegra_dc_state_setup_clock()
1857 state->pclk = pclk; in tegra_dc_state_setup_clock()
1858 state->div = div; in tegra_dc_state_setup_clock()
1870 if (!dc->has_opp_table) in tegra_dc_update_voltage_state()
1874 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); in tegra_dc_update_voltage_state()
1877 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); in tegra_dc_update_voltage_state()
1884 if (opp == ERR_PTR(-ERANGE)) in tegra_dc_update_voltage_state()
1885 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); in tegra_dc_update_voltage_state()
1888 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", in tegra_dc_update_voltage_state()
1899 * rate of the display controller clock. This is why we're not using in tegra_dc_update_voltage_state()
1903 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); in tegra_dc_update_voltage_state()
1905 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", in tegra_dc_update_voltage_state()
1914 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_set_clock_rate()
1916 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_set_clock_rate()
1920 * relevant to Tegra20 where only a single display PLL is available. in tegra_dc_set_clock_rate()
1926 if (state->pclk > 0) { in tegra_dc_set_clock_rate()
1927 err = clk_set_rate(state->clk, state->pclk); in tegra_dc_set_clock_rate()
1929 dev_err(dc->dev, in tegra_dc_set_clock_rate()
1931 state->pclk); in tegra_dc_set_clock_rate()
1933 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_set_clock_rate()
1935 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_set_clock_rate()
1936 dc->clk, state->pclk, err); in tegra_dc_set_clock_rate()
1939 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_set_clock_rate()
1940 state->div); in tegra_dc_set_clock_rate()
1941 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); in tegra_dc_set_clock_rate()
1950 /* stop the display controller */ in tegra_dc_stop()
1978 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1979 return -ETIMEDOUT; in tegra_dc_wait_idle()
1996 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
2001 if (!crtc->state->active) { in tegra_crtc_update_memory_bandwidth()
2002 if (!old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
2013 icc_set_bw(tegra->icc_mem, 0, 0); in tegra_crtc_update_memory_bandwidth()
2014 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
2020 for_each_old_plane_in_state(old_crtc_state->state, plane, in tegra_crtc_update_memory_bandwidth()
2023 new_tegra_state = to_const_tegra_plane_state(plane->state); in tegra_crtc_update_memory_bandwidth()
2031 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
2034 new_avg_bw = new_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2035 old_avg_bw = old_tegra_state->avg_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2037 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2038 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; in tegra_crtc_update_memory_bandwidth()
2041 * See the comment related to !crtc->state->active above, in tegra_crtc_update_memory_bandwidth()
2046 old_crtc_state->active) in tegra_crtc_update_memory_bandwidth()
2049 window.src.h = drm_rect_height(&plane->state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
2050 window.dst.h = drm_rect_height(&plane->state->dst); in tegra_crtc_update_memory_bandwidth()
2052 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; in tegra_crtc_update_memory_bandwidth()
2053 old_window.dst.h = drm_rect_height(&old_plane_state->dst); in tegra_crtc_update_memory_bandwidth()
2070 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
2073 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); in tegra_crtc_update_memory_bandwidth()
2075 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); in tegra_crtc_update_memory_bandwidth()
2098 * these bits has the side-effect of stopping the display controller. in tegra_crtc_atomic_disable()
2100 * time the encoder is disabled before the display controller, so the in tegra_crtc_atomic_disable()
2104 * Given the close coupling between the RGB encoder and the display in tegra_crtc_atomic_disable()
2108 * XXX: Perhaps given that the display controller is switched off at in tegra_crtc_atomic_disable()
2112 if (dc->rgb) { in tegra_crtc_atomic_disable()
2119 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
2122 spin_lock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
2124 if (crtc->state->event) { in tegra_crtc_atomic_disable()
2125 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_disable()
2126 crtc->state->event = NULL; in tegra_crtc_atomic_disable()
2129 spin_unlock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
2131 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
2133 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
2135 if (dc->has_opp_table) { in tegra_crtc_atomic_disable()
2136 err = dev_pm_genpd_set_performance_state(dc->dev, 0); in tegra_crtc_atomic_disable()
2138 dev_err(dc->dev, in tegra_crtc_atomic_disable()
2146 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in tegra_crtc_atomic_enable()
2147 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); in tegra_crtc_atomic_enable()
2155 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2157 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2161 /* initialize display controller */ in tegra_crtc_atomic_enable()
2162 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2163 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2165 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2177 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2224 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2230 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2231 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1; in tegra_crtc_atomic_enable()
2235 /* program display mode */ in tegra_crtc_atomic_enable()
2239 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2250 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2257 /* enable underflow reporting and display red for missing pixels */ in tegra_crtc_atomic_enable()
2258 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2263 if (dc->rgb) { in tegra_crtc_atomic_enable()
2281 if (crtc->state->event) { in tegra_crtc_atomic_begin()
2282 spin_lock_irqsave(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2285 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2287 drm_crtc_arm_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
2289 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
2291 crtc->state->event = NULL; in tegra_crtc_atomic_begin()
2304 value = dc_state->planes << 8 | GENERAL_UPDATE; in tegra_crtc_atomic_flush()
2308 value = dc_state->planes | GENERAL_ACT_REQ; in tegra_crtc_atomic_flush()
2315 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; in tegra_plane_is_cursor()
2316 const struct drm_format_info *fmt = state->fb->format; in tegra_plane_is_cursor()
2317 unsigned int src_w = drm_rect_width(&state->src) >> 16; in tegra_plane_is_cursor()
2318 unsigned int dst_w = drm_rect_width(&state->dst); in tegra_plane_is_cursor()
2320 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) in tegra_plane_is_cursor()
2323 if (soc->supports_cursor) in tegra_plane_is_cursor()
2326 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) in tegra_plane_is_cursor()
2342 if (!plane_state->visible || !plane_state->fb) in tegra_plane_overlap_mask()
2346 * Data-prefetch FIFO will easily help to overcome temporal memory in tegra_plane_overlap_mask()
2353 rect = plane_state->dst; in tegra_plane_overlap_mask()
2355 tegra = to_tegra_plane(other_state->plane); in tegra_plane_overlap_mask()
2357 if (!other_state->visible || !other_state->fb) in tegra_plane_overlap_mask()
2368 if (drm_rect_intersect(&rect, &other_state->dst)) in tegra_plane_overlap_mask()
2369 overlap_mask |= BIT(tegra->index); in tegra_plane_overlap_mask()
2390 * The nv-display uses shared planes. The algorithm below assumes in tegra_crtc_calculate_memory_bandwidth()
2391 * maximum 3 planes per-CRTC, this assumption isn't applicable to in tegra_crtc_calculate_memory_bandwidth()
2392 * the nv-display. Note that T124 support has additional windows, in tegra_crtc_calculate_memory_bandwidth()
2395 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2416 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) in tegra_crtc_calculate_memory_bandwidth()
2417 return -EINVAL; in tegra_crtc_calculate_memory_bandwidth()
2419 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2421 overlap_mask[tegra->index] = mask; in tegra_crtc_calculate_memory_bandwidth()
2431 * fetches from the planes simultaneously during of scan-out process. in tegra_crtc_calculate_memory_bandwidth()
2435 * A-and-B or A-and-C planes overlap. in tegra_crtc_calculate_memory_bandwidth()
2454 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { in tegra_crtc_calculate_memory_bandwidth()
2455 if (i == tegra->index) in tegra_crtc_calculate_memory_bandwidth()
2464 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; in tegra_crtc_calculate_memory_bandwidth()
2465 old_peak_bw = tegra_state->total_peak_memory_bandwidth; in tegra_crtc_calculate_memory_bandwidth()
2482 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; in tegra_crtc_calculate_memory_bandwidth()
2505 * Display bandwidth is allowed to go down only once hardware state in tegra_crtc_atomic_post_commit()
2530 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
2532 dc->stats.frames_total++; in tegra_dc_irq()
2533 dc->stats.frames++; in tegra_dc_irq()
2538 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
2540 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2541 dc->stats.vblank_total++; in tegra_dc_irq()
2542 dc->stats.vblank++; in tegra_dc_irq()
2547 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
2549 dc->stats.underflow_total++; in tegra_dc_irq()
2550 dc->stats.underflow++; in tegra_dc_irq()
2555 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2557 dc->stats.overflow_total++; in tegra_dc_irq()
2558 dc->stats.overflow++; in tegra_dc_irq()
2562 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2563 dc->stats.underflow_total++; in tegra_dc_irq()
2564 dc->stats.underflow++; in tegra_dc_irq()
2574 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2577 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2578 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2580 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2589 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_early_init()
2590 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_early_init()
2592 tegra->num_crtcs++; in tegra_dc_early_init()
2599 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_init()
2602 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_init()
2611 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2622 * Set the display hub as the host1x client parent for the display in tegra_dc_init()
2624 * ensures the display hub is always powered when any of the display in tegra_dc_init()
2627 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2628 client->parent = &tegra->hub->client; in tegra_dc_init()
2630 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2631 if (!dc->syncpt) in tegra_dc_init()
2632 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2635 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2636 dev_err(client->dev, "failed to attach to domain: %d\n", err); in tegra_dc_init()
2640 if (dc->soc->wgrps) in tegra_dc_init()
2650 if (dc->soc->supports_cursor) { in tegra_dc_init()
2665 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2670 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2673 * Keep track of the minimum pitch alignment across all display in tegra_dc_init()
2676 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2677 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2680 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2681 drm->mode_config.max_width = drm->mode_config.max_height = 16384; in tegra_dc_init()
2683 drm->mode_config.max_width = drm->mode_config.max_height = 4096; in tegra_dc_init()
2686 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2687 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2691 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2692 dev_name(dc->dev), dc); in tegra_dc_init()
2694 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2703 client->dev->dma_parms = client->host->dma_parms; in tegra_dc_init()
2715 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2729 client->dev->dma_parms = NULL; in tegra_dc_exit()
2731 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2735 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2740 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2747 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_late_exit()
2748 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_late_exit()
2750 tegra->num_crtcs--; in tegra_dc_late_exit()
2758 struct device *dev = client->dev; in tegra_dc_runtime_suspend()
2761 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2767 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2768 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2770 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2779 struct device *dev = client->dev; in tegra_dc_runtime_resume()
2788 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2789 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2790 dc->rst); in tegra_dc_runtime_resume()
2796 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2802 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2812 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
3046 .compatible = "nvidia,tegra194-dc",
3049 .compatible = "nvidia,tegra186-dc",
3052 .compatible = "nvidia,tegra210-dc",
3055 .compatible = "nvidia,tegra124-dc",
3058 .compatible = "nvidia,tegra114-dc",
3061 .compatible = "nvidia,tegra30-dc",
3064 .compatible = "nvidia,tegra20-dc",
3078 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
3080 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
3085 * display controller's node within the device tree. Assuming in tegra_dc_parse_dt()
3092 * cases where only a single display controller is used. in tegra_dc_parse_dt()
3095 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
3104 dc->pipe = value; in tegra_dc_parse_dt()
3114 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
3124 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
3128 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
3131 return -EPROBE_DEFER; in tegra_dc_couple()
3134 dc->client.parent = &parent->client; in tegra_dc_couple()
3136 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
3147 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); in tegra_dc_init_opp_table()
3148 if (err && err != -ENODEV) in tegra_dc_init_opp_table()
3152 dc->has_opp_table = false; in tegra_dc_init_opp_table()
3154 dc->has_opp_table = true; in tegra_dc_init_opp_table()
3161 u64 dma_mask = dma_get_mask(pdev->dev.parent); in tegra_dc_probe()
3165 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); in tegra_dc_probe()
3167 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); in tegra_dc_probe()
3171 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
3173 return -ENOMEM; in tegra_dc_probe()
3175 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
3177 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
3178 dc->dev = &pdev->dev; in tegra_dc_probe()
3188 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3189 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3190 dev_err(&pdev->dev, "failed to get clock\n"); in tegra_dc_probe()
3191 return PTR_ERR(dc->clk); in tegra_dc_probe()
3194 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3195 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3196 dev_err(&pdev->dev, "failed to get reset\n"); in tegra_dc_probe()
3197 return PTR_ERR(dc->rst); in tegra_dc_probe()
3201 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3207 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3213 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3215 if (dc->soc->has_powergate) { in tegra_dc_probe()
3216 if (dc->pipe == 0) in tegra_dc_probe()
3217 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3219 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3221 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3228 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3229 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3230 return PTR_ERR(dc->regs); in tegra_dc_probe()
3232 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3233 if (dc->irq < 0) in tegra_dc_probe()
3234 return -ENXIO; in tegra_dc_probe()
3237 if (err < 0 && err != -ENODEV) in tegra_dc_probe()
3238 return dev_err_probe(&pdev->dev, err, in tegra_dc_probe()
3242 pm_runtime_enable(&pdev->dev); in tegra_dc_probe()
3244 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3245 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3246 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3248 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3250 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dc_probe()
3258 pm_runtime_disable(&pdev->dev); in tegra_dc_probe()
3269 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
3271 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", in tegra_dc_remove()
3278 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); in tegra_dc_remove()
3282 pm_runtime_disable(&pdev->dev); in tegra_dc_remove()
3289 .name = "tegra-dc",