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/Linux-v6.1/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
[all …]
/Linux-v6.1/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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Dtegra186-p3310.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra186.dtsi"
4 #include <dt-bindings/mfd/max77620.h>
8 compatible = "nvidia,p3310", "nvidia,tegra186";
27 stdout-path = "serial0:115200n8";
38 phy-reset-gpios = <&gpio TEGRA186_MAIN_GPIO(M, 4)
40 phy-handle = <&phy>;
41 phy-mode = "rgmii";
44 #address-cells = <1>;
45 #size-cells = <0>;
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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Dtegra186-p3509-0000+p3636-0001.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/linux-event-codes.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra186.dtsi"
12 compatible = "nvidia,p3509-0000+p3636-0001", "nvidia,tegra186";
30 stdout-path = "serial0:115200n8";
41 phy-reset-gpios = <&gpio_aon TEGRA186_AON_GPIO(AA, 6) GPIO_ACTIVE_LOW>;
42 phy-handle = <&phy>;
[all …]
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/power/tegra234-powergate.h>
9 #include <dt-bindings/reset/tegra234-reset.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
[all …]
/Linux-v6.1/drivers/soc/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += fuse/
3 obj-y += cbb/
5 obj-y += common.o
6 obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o
7 obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o
8 obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o
9 obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o
10 obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o
11 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += ari-tegra186.o
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
52 #include <soc/tegra/pmc.h>
54 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dnvidia,tegra124-xusb.txt8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
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/Linux-v6.1/drivers/gpio/
Dgpio-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2022 NVIDIA Corporation
17 #include <dt-bindings/gpio/tegra186-gpio.h>
18 #include <dt-bindings/gpio/tegra194-gpio.h>
19 #include <dt-bindings/gpio/tegra234-gpio.h>
20 #include <dt-bindings/gpio/tegra241-gpio.h>
103 for (i = 0; i < gpio->soc->num_ports; i++) { in tegra186_gpio_get_port()
104 const struct tegra_gpio_port *port = &gpio->soc->ports[i]; in tegra186_gpio_get_port()
106 if (*pin >= start && *pin < start + port->pins) { in tegra186_gpio_get_port()
107 *pin -= start; in tegra186_gpio_get_port()
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/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
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/Linux-v6.1/drivers/gpu/drm/tegra/
Dnvdec.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2021, NVIDIA Corporation.
8 #include <linux/dma-mapping.h>
19 #include <soc/tegra/pmc.h>
54 writel(value, nvdec->regs + offset); in nvdec_writel()
60 struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev); in nvdec_boot()
65 if (nvdec->config->supports_sid && spec) { in nvdec_boot()
71 if (spec->num_ids > 0) { in nvdec_boot()
72 value = spec->ids[0] & 0xffff; in nvdec_boot()
80 err = falcon_boot(&nvdec->falcon); in nvdec_boot()
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Dvic.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
19 #include <soc/tegra/pmc.h>
54 writel(value, vic->regs + offset); in vic_writel()
60 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); in vic_boot()
67 if (vic->config->supports_sid && spec) { in vic_boot()
74 if (spec->num_ids > 0) { in vic_boot()
75 value = spec->ids[0] & 0xffff; in vic_boot()
101 err = falcon_boot(&vic->falcon); in vic_boot()
105 hdr = vic->falcon.firmware.virt; in vic_boot()
[all …]
Dsor.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 #include <soc/tegra/pmc.h>
486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
504 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
506 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
510 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
[all …]
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
21 #include <soc/tegra/pmc.h>
42 stats->frames = 0; in tegra_dc_stats_reset()
43 stats->vblank = 0; in tegra_dc_stats_reset()
44 stats->underflow = 0; in tegra_dc_stats_reset()
45 stats->overflow = 0; in tegra_dc_stats_reset()
64 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
65 return plane->offset + offset; in tegra_plane_offset()
69 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
[all …]
/Linux-v6.1/drivers/ata/
Dahci_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
184 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks()
187 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
196 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init()
208 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
210 val = readl(tegra->sata_regs + in tegra124_ahci_init()
[all …]
/Linux-v6.1/drivers/clk/tegra/
Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
20 #include <soc/tegra/pmc.h>
23 #include "clk-id.h"
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
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/Linux-v6.1/drivers/usb/host/
Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
11 #include <linux/dma-mapping.h>
32 #include <soc/tegra/pmc.h>
283 return readl(tegra->fpci_base + offset); in fpci_readl()
289 writel(value, tegra->fpci_base + offset); in fpci_writel()
294 return readl(tegra->ipfs_base + offset); in ipfs_readl()
300 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
327 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()
341 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
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/Linux-v6.1/drivers/pci/controller/
Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
44 #include <soc/tegra/pmc.h>
256 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
378 writel(value, pcie->afi + offset); in afi_writel()
383 return readl(pcie->afi + offset); in afi_readl()
389 writel(value, pcie->pads + offset); in pads_writel()
394 return readl(pcie->pads + offset); in pads_readl()
429 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus()
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