Searched full:synchronised (Results 1 – 25 of 39) sorted by relevance
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6 * All CPUs will have their count registers synchronised to the CPU0 next time42 * then the last pass is more or less synchronised and in synchronise_count_master()
5 * All CPUs will have their count registers synchronised to the CPU0 next time39 * then the last pass is more or less synchronised and in synchronise_count_master()
365 /* The CPU is running and counters synchronised, now mark it online */ in start_secondary()
34 Synchronised LED flash (hardware strobe)37 The synchronised LED flash is pre-programmed by the host (power and
126 - Byte 0: bit 0: depth and RGB are synchronised, bit 1: external trigger
146 * If we have already synchronised this @root timeline with another (@id) then151 * Returns true if the two timelines are already synchronised wrt to @seqno,343 * @id: the context id (other timeline) we have synchronised to
27 GPIO numbering is synchronised between the Samsung and gpiolib system.
72 * accesses) are properly synchronised with writes to DMA coherent memory79 * Note: the SRAM path is not synchronised via mb() and wmb().
45 synchronised mode for all channels it has been synthesised for.
48 /* The host page table is installed, but not yet synchronised */ in __debug_restore_spe()
97 * tells you if an area is synchronised, the other
5 * Synchronised with arm_mhu.c from :
83 * - the datum will be synchronised to the server if AT_STATX_FORCE_SYNC is
56 * an Interval Timer of its own and they are not synchronised.
228 * synchronised ADC conversions (via the ADCSYNC pin) must wait234 * If called for a synchronised ADC conversion, it may sleep
278 0: All types of connections are synchronised
107 * subcores have separate timebases SPRs but these are pre-synchronised by
156 * The page tables are fully synchronised so there must in vmalloc_sync_one()
29 * synchronised.
161 * Conversions are synchronised on the rising edge of NAU7802_PUCTRL_CS_BIT
262 * Harvard caches are synchronised for the user space address range.
139 * removed from the IDR (and RCU synchronised) it's safe to free the in afu_release()
149 * synchronised with the server.
1447 * A source-synchronised channel is one where the fetching of data is in omap_dma_pause()1449 * transfer. So, a destination-synchronised channel (which would be a in omap_dma_pause()
