Searched +full:stratix10 +full:- +full:clkmgr (Results 1 – 6 of 6) sorted by relevance
| /Linux-v6.1/Documentation/devicetree/bindings/clock/ |
| D | intel,stratix10.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel SoCFPGA Stratix10 platform clock controller binding
10 - Dinh Nguyen <dinguyen@kernel.org>
14 const: intel,stratix10-clkmgr
16 '#clock-cells':
23 - compatible
24 - reg
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| /Linux-v6.1/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| D | socfpga_stratix10_swvp.dts | 1 // SPDX-License-Identifier: GPL-2.0
10 compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
27 stdout-path = "serial1:115200n8";
28 linux,initrd-start = <0x10000000>;
29 linux,initrd-end = <0x125c8324>;
39 enable-method = "spin-table";
40 cpu-release-addr = <0x0 0x0000fff8>;
44 enable-method = "spin-table";
45 cpu-release-addr = <0x0 0x0000fff8>;
49 enable-method = "spin-table";
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| /Linux-v6.1/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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| /Linux-v6.1/drivers/clk/socfpga/ |
| D | clk-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/stratix10-clock.h>
13 #include "stratix10-clk.h"
18 { .fw_name = "cb-intosc-hs-div2-clk",
19 .name = "cb-intosc-hs-div2-clk" },
20 { .fw_name = "f2s-free-clk",
21 .name = "f2s-free-clk" },
31 { .fw_name = "cb-intosc-hs-div2-clk",
32 .name = "cb-intosc-hs-div2-clk", },
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| D | clk-agilex.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/agilex-clock.h>
13 #include "stratix10-clk.h"
18 { .fw_name = "cb-intosc-hs-div2-clk",
19 .name = "cb-intosc-hs-div2-clk", },
20 { .fw_name = "f2s-free-clk",
21 .name = "f2s-free-clk", },
27 { .fw_name = "cb-intosc-hs-div2-clk",
28 .name = "cb-intosc-hs-div2-clk", },
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