1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/agilex-clock.h>
13 #include "stratix10-clk.h"
18 	{ .fw_name = "cb-intosc-hs-div2-clk",
19 	  .name = "cb-intosc-hs-div2-clk", },
20 	{ .fw_name = "f2s-free-clk",
21 	  .name = "f2s-free-clk", },
27 	{ .fw_name = "cb-intosc-hs-div2-clk",
28 	  .name = "cb-intosc-hs-div2-clk", },
38 	{ .fw_name = "cb-intosc-hs-div2-clk",
39 	  .name = "cb-intosc-hs-div2-clk", },
40 	{ .fw_name = "f2s-free-clk",
41 	  .name = "f2s-free-clk", },
51 	{ .fw_name = "cb-intosc-hs-div2-clk",
52 	  .name = "cb-intosc-hs-div2-clk", },
53 	{ .fw_name = "f2s-free-clk",
54 	  .name = "f2s-free-clk", },
64 	{ .fw_name = "cb-intosc-hs-div2-clk",
65 	  .name = "cb-intosc-hs-div2-clk", },
66 	{ .fw_name = "f2s-free-clk",
67 	  .name = "f2s-free-clk", },
77 	{ .fw_name = "cb-intosc-hs-div2-clk",
78 	  .name = "cb-intosc-hs-div2-clk", },
79 	{ .fw_name = "f2s-free-clk",
80 	  .name = "f2s-free-clk", },
90 	{ .fw_name = "cb-intosc-hs-div2-clk",
91 	  .name = "cb-intosc-hs-div2-clk", },
92 	{ .fw_name = "f2s-free-clk",
93 	  .name = "f2s-free-clk", },
103 	{ .fw_name = "cb-intosc-hs-div2-clk",
104 	  .name = "cb-intosc-hs-div2-clk", },
105 	{ .fw_name = "f2s-free-clk",
106 	  .name = "f2s-free-clk", },
116 	{ .fw_name = "cb-intosc-hs-div2-clk",
117 	  .name = "cb-intosc-hs-div2-clk", },
118 	{ .fw_name = "f2s-free-clk",
119 	  .name = "f2s-free-clk", },
129 	{ .fw_name = "cb-intosc-hs-div2-clk",
130 	  .name = "cb-intosc-hs-div2-clk", },
131 	{ .fw_name = "f2s-free-clk",
132 	  .name = "f2s-free-clk", },
142 	{ .fw_name = "cb-intosc-hs-div2-clk",
143 	  .name = "cb-intosc-hs-div2-clk", },
144 	{ .fw_name = "f2s-free-clk",
145 	  .name = "f2s-free-clk", },
155 	{ .fw_name = "cb-intosc-hs-div2-clk",
156 	  .name = "cb-intosc-hs-div2-clk", },
157 	{ .fw_name = "f2s-free-clk",
158 	  .name = "f2s-free-clk", },
342 	void __iomem *base = data->base;  in n5x_clk_register_c_perip()
352 		data->clk_data.hws[clks[i].id] = hw_clk;  in n5x_clk_register_c_perip()
361 	void __iomem *base = data->base;  in agilex_clk_register_c_perip()
371 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_c_perip()
380 	void __iomem *base = data->base;  in agilex_clk_register_cnt_perip()
390 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_cnt_perip()
400 	void __iomem *base = data->base;  in agilex_clk_register_gate()
410 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_gate()
420 	void __iomem *base = data->base;  in agilex_clk_register_pll()
430 		data->clk_data.hws[clks[i].id] = hw_clk;  in agilex_clk_register_pll()
440 	void __iomem *base = data->base;  in n5x_clk_register_pll()
450 		data->clk_data.hws[clks[i].id] = hw_clk;  in n5x_clk_register_pll()
458 	struct device_node *np = pdev->dev.of_node;  in agilex_clkmgr_init()
459 	struct device *dev = &pdev->dev;  in agilex_clkmgr_init()
475 		return -ENOMEM;  in agilex_clkmgr_init()
478 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);  in agilex_clkmgr_init()
480 	clk_data->base = base;  in agilex_clkmgr_init()
481 	clk_data->clk_data.num = num_clks;  in agilex_clkmgr_init()
494 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);  in agilex_clkmgr_init()
500 	struct device_node *np = pdev->dev.of_node;  in n5x_clkmgr_init()
501 	struct device *dev = &pdev->dev;  in n5x_clkmgr_init()
515 		return -ENOMEM;  in n5x_clkmgr_init()
518 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);  in n5x_clkmgr_init()
520 	clk_data->base = base;  in n5x_clkmgr_init()
521 	clk_data->clk_data.num = num_clks;  in n5x_clkmgr_init()
534 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);  in n5x_clkmgr_init()
542 	probe_func = of_device_get_match_data(&pdev->dev);  in agilex_clkmgr_probe()
544 		return -ENODEV;  in agilex_clkmgr_probe()
549 	{ .compatible = "intel,agilex-clkmgr",
551 	{ .compatible = "intel,easic-n5x-clkmgr",
559 		.name	= "agilex-clkmgr",