Searched +full:stm32f4 +full:- +full:adc (Results 1 – 7 of 7) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"7 title: STMicroelectronics STM32 ADC bindings10 STM32 ADC is a successive approximation analog-to-digital converter.12 in single, continuous, scan or discontinuous mode. Result of the ADC is13 stored in a left-aligned or right-aligned 32-bit data register.17 voltage goes beyond the user-defined, higher or lower thresholds.19 Each STM32 ADC block can have up to 3 ADC instances.[all …]
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>4 * This file is dual-licensed: you can use it either under the terms22 * MA 02110-1301 USA48 #include "armv7-m.dtsi"49 #include <dt-bindings/clock/stm32fx-clock.h>50 #include <dt-bindings/mfd/stm32f4-rcc.h>53 #address-cells = <1>;54 #size-cells = <1>;57 clk_hse: clk-hse {58 #clock-cells = <0>;[all …]
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>4 * This file is dual-licensed: you can use it either under the terms43 #include <dt-bindings/pinctrl/stm32-pinfunc.h>44 #include <dt-bindings/mfd/stm32f4-rcc.h>49 #address-cells = <1>;50 #size-cells = <1>;52 interrupt-parent = <&exti>;54 pins-are-numbered;57 gpio-controller;58 #gpio-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * This file is part of STM32 ADC driver5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved8 * Inspired from: fsl-imx25-tsadc26 #include "stm32-adc-core.h"42 * struct stm32_adc_common_regs - stm32 common registers47 * @ier: interrupt enable register offset for each adc62 * struct stm32_adc_priv_cfg - stm32 core compatible configuration data66 * @ipid: adc identification number69 * @num_adcs: maximum number of ADC instances in the common registers[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * This file is part of STM32 ADC driver5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved14 * STM32 - ADC global register map17 * --------------------------------------------------------19 * --------------------------------------------------------21 * --------------------------------------------------------23 * --------------------------------------------------------25 * --------------------------------------------------------27 /* Maximum ADC instances number per ADC block for all supported SoCs */[all …]
1 // SPDX-License-Identifier: GPL-2.03 * This file is part of STM32 ADC driver5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved11 #include <linux/dma-mapping.h>15 #include <linux/iio/timer/stm32-lptim-trigger.h>16 #include <linux/iio/timer/stm32-timer-trigger.h>25 #include <linux/nvmem-consumer.h>30 #include "stm32-adc-core.h"35 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */57 /* extsel - trigger mux selection value */[all …]
1 /* SPDX-License-Identifier: GPL-2.0-only */7 * NOTE: This file is auto-generated from ChromeOS EC Open Source code from52 * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff77 #define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */78 #define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */79 #define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */81 #define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */82 #define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */83 #define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */84 #define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */[all …]
