Lines Matching +full:stm32f4 +full:- +full:adc
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
84 compatible = "st,stm32f4-otp";
86 #address-cells = <1>;
87 #size-cells = <1>;
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "st,stm32-timers";
102 clock-names = "int";
106 compatible = "st,stm32-pwm";
107 #pwm-cells = <3>;
112 compatible = "st,stm32-timer-trigger";
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
124 clock-names = "int";
128 compatible = "st,stm32-pwm";
129 #pwm-cells = <3>;
134 compatible = "st,stm32-timer-trigger";
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "st,stm32-timers";
146 clock-names = "int";
150 compatible = "st,stm32-pwm";
151 #pwm-cells = <3>;
156 compatible = "st,stm32-timer-trigger";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "st,stm32-timers";
168 clock-names = "int";
172 compatible = "st,stm32-pwm";
173 #pwm-cells = <3>;
178 compatible = "st,stm32-timer-trigger";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "st,stm32-timers";
190 clock-names = "int";
194 compatible = "st,stm32-timer-trigger";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "st,stm32-timers";
206 clock-names = "int";
210 compatible = "st,stm32-timer-trigger";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 compatible = "st,stm32-timers";
222 clock-names = "int";
226 compatible = "st,stm32-pwm";
227 #pwm-cells = <3>;
232 compatible = "st,stm32-timer-trigger";
239 compatible = "st,stm32-timers";
242 clock-names = "int";
246 compatible = "st,stm32-pwm";
247 #pwm-cells = <3>;
253 compatible = "st,stm32-timers";
256 clock-names = "int";
260 compatible = "st,stm32-pwm";
261 #pwm-cells = <3>;
267 compatible = "st,stm32-rtc";
270 assigned-clocks = <&rcc 1 CLK_RTC>;
271 assigned-clock-parents = <&rcc 1 CLK_LSE>;
272 interrupt-parent = <&exti>;
279 compatible = "st,stm32-iwdg";
282 clock-names = "lsi";
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32f4-spi";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "st,stm32f4-spi";
307 compatible = "st,stm32-uart";
315 compatible = "st,stm32-uart";
322 dma-names = "rx", "tx";
326 compatible = "st,stm32-uart";
334 compatible = "st,stm32-uart";
342 compatible = "st,stm32f4-i2c";
348 #address-cells = <1>;
349 #size-cells = <0>;
354 compatible = "st,stm32f4-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
366 compatible = "st,stm32f4-dac-core";
370 clock-names = "pclk";
371 #address-cells = <1>;
372 #size-cells = <0>;
376 compatible = "st,stm32-dac";
377 #io-channel-cells = <1>;
383 compatible = "st,stm32-dac";
384 #io-channel-cells = <1>;
391 compatible = "st,stm32-uart";
399 compatible = "st,stm32-uart";
407 #address-cells = <1>;
408 #size-cells = <0>;
409 compatible = "st,stm32-timers";
412 clock-names = "int";
416 compatible = "st,stm32-pwm";
417 #pwm-cells = <3>;
422 compatible = "st,stm32-timer-trigger";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "st,stm32-timers";
434 clock-names = "int";
438 compatible = "st,stm32-pwm";
439 #pwm-cells = <3>;
444 compatible = "st,stm32-timer-trigger";
451 compatible = "st,stm32-uart";
458 dma-names = "rx", "tx";
462 compatible = "st,stm32-uart";
469 adc: adc@40012000 { label
470 compatible = "st,stm32f4-adc-core";
474 clock-names = "adc";
475 interrupt-controller;
476 #interrupt-cells = <1>;
477 #address-cells = <1>;
478 #size-cells = <0>;
481 adc1: adc@0 {
482 compatible = "st,stm32f4-adc";
483 #io-channel-cells = <1>;
486 interrupt-parent = <&adc>;
489 dma-names = "rx";
493 adc2: adc@100 {
494 compatible = "st,stm32f4-adc";
495 #io-channel-cells = <1>;
498 interrupt-parent = <&adc>;
501 dma-names = "rx";
505 adc3: adc@200 {
506 compatible = "st,stm32f4-adc";
507 #io-channel-cells = <1>;
510 interrupt-parent = <&adc>;
513 dma-names = "rx";
520 arm,primecell-periphid = <0x00880180>;
523 clock-names = "apb_pclk";
525 max-frequency = <48000000>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 compatible = "st,stm32f4-spi";
540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "st,stm32f4-spi";
550 compatible = "st,stm32-syscfg", "syscon";
554 exti: interrupt-controller@40013c00 {
555 compatible = "st,stm32-exti";
556 interrupt-controller;
557 #interrupt-cells = <2>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 compatible = "st,stm32-timers";
568 clock-names = "int";
572 compatible = "st,stm32-pwm";
573 #pwm-cells = <3>;
578 compatible = "st,stm32-timer-trigger";
585 compatible = "st,stm32-timers";
588 clock-names = "int";
592 compatible = "st,stm32-pwm";
593 #pwm-cells = <3>;
599 compatible = "st,stm32-timers";
602 clock-names = "int";
606 compatible = "st,stm32-pwm";
607 #pwm-cells = <3>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615 compatible = "st,stm32f4-spi";
621 dma-names = "rx", "tx";
626 #address-cells = <1>;
627 #size-cells = <0>;
628 compatible = "st,stm32f4-spi";
635 pwrcfg: power-config@40007000 {
636 compatible = "st,stm32-power-config", "syscon";
640 ltdc: display-controller@40016800 {
641 compatible = "st,stm32-ltdc";
646 clock-names = "lcd";
651 compatible = "st,stm32f4-crc";
658 #reset-cells = <1>;
659 #clock-cells = <2>;
660 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
664 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
665 assigned-clock-rates = <1000000>;
668 dma1: dma-controller@40026000 {
669 compatible = "st,stm32-dma";
680 #dma-cells = <4>;
683 dma2: dma-controller@40026400 {
684 compatible = "st,stm32-dma";
695 #dma-cells = <4>;
700 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
702 reg-names = "stmmaceth";
704 interrupt-names = "macirq";
705 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
711 snps,mixed-burst;
716 compatible = "st,stm32-dma2d";
721 clock-names = "dma2d";
730 clock-names = "otg";
735 compatible = "st,stm32f4x9-fsotg";
739 clock-names = "otg";
744 compatible = "st,stm32-dcmi";
749 clock-names = "mclk";
750 pinctrl-names = "default";
751 pinctrl-0 = <&dcmi_pins>;
753 dma-names = "tx";
758 compatible = "st,stm32-rng";