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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy@[0-9a-f]+$"
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/Linux-v5.15/Documentation/devicetree/bindings/media/
Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
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/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll() local
73 clock = ref * N1 / M1; in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
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/Linux-v5.15/drivers/net/can/mscan/
Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
19 #include <linux/clk.h>
36 { .compatible = "fsl,mpc5200-cdm", },
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
74 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
80 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
84 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
86 val = in_be32(&cdm->rstcfg); in mpc52xx_can_get_clock()
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/Linux-v5.15/drivers/phy/mediatek/
Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk.h>
86 #define XSP_REF_CLK 26 /* MHZ */
94 struct clk *ref_clk; /* reference clock of anolog phy */
112 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
119 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
125 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
168 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
175 dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in u2_phy_slew_rate_calibrate()
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Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
21 /* version V1 sub-banks offset base address */
32 /* version V2/V3 sub-banks offset base address */
221 #define U3P_REF_CLK 26 /* MHZ */
228 /* CDR Charge Pump P-path current adjustment */
254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
266 /* I-path capacitance adjustment for Gen1 */
353 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
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/Linux-v5.15/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
38 *------------------------------------------
39 * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
40 *------------------------------------------
42 *------------------------------------------
44 *------------------------------------------
46 *------------------------------------------
48 *------------------------------------------
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/Linux-v5.15/drivers/phy/
Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/Linux-v5.15/drivers/gpu/drm/gma500/
Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
117 ret__ = -ETIMEDOUT; \
216 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
230 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ in cdv_dpll_set_clock_cdv()
239 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk in cdv_dpll_set_clock_cdv()
247 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA in cdv_dpll_set_clock_cdv()
271 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
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/Linux-v5.15/sound/soc/codecs/
Drt5682.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
26 #include <sound/soc-dapm.h>
55 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
744 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
745 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
812 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
813 if (!rt5682->is_sdw) in rt5682_reset()
814 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
819 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
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Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
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Drt5668.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5668.c -- RT5668B ALSA SoC audio component driver
27 #include <sound/soc-dapm.h>
746 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
747 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
748 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
803 * rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters
827 return -EINVAL; in rt5668_sel_asrc_clk_src()
887 * rt5668_headset_detect - Detect headset.
922 rt5668->jack_type = SND_JACK_HEADSET; in rt5668_headset_detect()
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Dmt6351.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6351.c -- mt6351 ALSA SoC audio codec driver
8 #include <linux/dma-mapping.h>
202 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
204 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
225 dev_warn(cmpnt->dev, "%s(), error rate %d, return 3", in get_cap_reg_val()
256 dev_warn(cmpnt->dev, "%s(), error rate %d, return 8", in get_play_reg_val()
266 struct snd_soc_component *cmpnt = dai->component; in mt6351_codec_dai_hw_params()
270 dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n", in mt6351_codec_dai_hw_params()
271 __func__, substream->stream, rate); in mt6351_codec_dai_hw_params()
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Drt5665.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
27 #include <sound/soc-dapm.h>
888 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
890 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
891 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
892 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
893 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
895 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
48 clk_mgr->ctx->logger
52 /* ClocksStateInvalid - should not be used */
54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
64 /*ClocksStateInvalid - should not be used*/
66 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
76 /*ClocksStateInvalid - should not be used*/
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/Linux-v5.15/drivers/comedi/drivers/
Dadv_pci1710.c1 // SPDX-License-Identifier: GPL-2.0
4 * Comedi driver for Advantech PCI-1710 series boards
13 * Description: Comedi driver for Advantech PCI-1710 series boards
14 * Devices: [Advantech] PCI-1710 (adv_pci1710), PCI-1710HG, PCI-1711,
15 * PCI-1713, PCI-1731
17 * Updated: Fri, 29 Oct 2015 17:19:35 -0700
26 * The PCI-1710 and PCI-1710HG have the same PCI device ID, so the
40 * PCI BAR2 Register map (dev->iobase)
58 #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */
118 UNI_RANGE(5), /* internal -5V ref */
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/Linux-v5.15/arch/arm/boot/dts/
Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
50 #address-cells = <1>;
51 #size-cells = <0>;
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/Linux-v5.15/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser2.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
69 bp->base.ctx->logger
112 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
116 kfree(bp->base.bios_local_image); in bios_parser2_destruct()
117 kfree(bp->base.integrated_info); in bios_parser2_destruct()
143 tbl_revision->major = 0; in get_atom_data_table_revision()
144 tbl_revision->minor = 0; in get_atom_data_table_revision()
149 tbl_revision->major = in get_atom_data_table_revision()
150 (uint32_t) atom_data_tbl->format_revision & 0x3f; in get_atom_data_table_revision()
151 tbl_revision->minor = in get_atom_data_table_revision()
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/Linux-v5.15/drivers/misc/habanalabs/common/
Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2019 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
33 * bits[63:61] - Encode mmap type
34 * bits[45:0] - mmap offset value
39 #define HL_MMAP_TYPE_SHIFT (61 - PAGE_SHIFT)
81 * enum hl_mmu_page_table_locaion - mmu page table location
82 * @MMU_DR_PGT: page-table is located on device DRAM.
83 * @MMU_HR_PGT: page-table is located on host memory.
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/Linux-v5.15/drivers/net/ethernet/sfc/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/Linux-v5.15/drivers/gpu/drm/i915/
Di915_reg.h18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
120 * REG_BIT() - Prepare a u32 bit value
121 * @__n: 0-based bit number
133 * REG_GENMASK() - Prepare a continuous u32 bitmask
134 * @__high: 0-based high bit
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/Linux-v5.15/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c276 /* TA_GRAD_ADJ_UCONFIG -> TA_GRAD_ADJ */
278 /* VGT_TF_RING_SIZE_UMD -> VGT_TF_RING_SIZE */
280 /* VGT_HS_OFFCHIP_PARAM_UMD -> VGT_HS_OFFCHIP_PARAM */
282 /* VGT_TF_MEMORY_BASE_UMD -> VGT_TF_MEMORY_BASE */
284 /* VGT_TF_MEMORY_BASE_HI_UMD -> VGT_TF_MEMORY_BASE_HI */
286 /* VGT_ESGS_RING_SIZE_UMD -> VGT_ESGS_RING_SIZE */
288 /* VGT_GSVS_RING_SIZE_UMD -> VGT_GSVS_RING_SIZE */
1531 scratch_reg0 = adev->rmmio + in gfx_v10_rlcg_rw()
1532 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4; in gfx_v10_rlcg_rw()
1533 scratch_reg1 = adev->rmmio + in gfx_v10_rlcg_rw()
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