Lines Matching +full:src +full:- +full:ref +full:- +full:clk +full:- +full:mhz
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
46 #include <linux/clk.h>
85 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) argument
94 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
95 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
96 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
97 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
99 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
100 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
102 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
103 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
109 #define CFG_IND_ADDR_SET(dst, src) \ argument
110 (((dst) & ~0x003ffff0) | (((u32) (src) << 4) & 0x003ffff0))
114 #define I_RESET_B_SET(dst, src) \ argument
115 (((dst) & ~0x00000001) | (((u32) (src)) & 0x00000001))
116 #define I_PLL_FBDIV_SET(dst, src) \ argument
117 (((dst) & ~0x001ff000) | (((u32) (src) << 12) & 0x001ff000))
118 #define I_CUSTOMEROV_SET(dst, src) \ argument
119 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
120 #define O_PLL_LOCK_RD(src) (((src) & 0x40000000) >> 30) argument
121 #define O_PLL_READY_RD(src) (((src) & 0x80000000) >> 31) argument
126 #define CMU_REG0_PLL_REF_SEL_SET(dst, src) \ argument
127 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
129 #define CMU_REG0_CAL_COUNT_RESOL_SET(dst, src) \ argument
130 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
132 #define CMU_REG1_PLL_CP_SET(dst, src) \ argument
133 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
134 #define CMU_REG1_PLL_MANUALCAL_SET(dst, src) \ argument
135 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
136 #define CMU_REG1_PLL_CP_SEL_SET(dst, src) \ argument
137 (((dst) & ~0x000003e0) | (((u32) (src) << 5) & 0x000003e0))
139 #define CMU_REG1_REFCLK_CMOS_SEL_SET(dst, src) \ argument
140 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
142 #define CMU_REG2_PLL_REFDIV_SET(dst, src) \ argument
143 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
144 #define CMU_REG2_PLL_LFRES_SET(dst, src) \ argument
145 (((dst) & ~0x0000001e) | (((u32) (src) << 1) & 0x0000001e))
146 #define CMU_REG2_PLL_FBDIV_SET(dst, src) \ argument
147 (((dst) & ~0x00003fe0) | (((u32) (src) << 5) & 0x00003fe0))
149 #define CMU_REG3_VCOVARSEL_SET(dst, src) \ argument
150 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
151 #define CMU_REG3_VCO_MOMSEL_INIT_SET(dst, src) \ argument
152 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
153 #define CMU_REG3_VCO_MANMOMSEL_SET(dst, src) \ argument
154 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
157 #define CMU_REG5_PLL_LFSMCAP_SET(dst, src) \ argument
158 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
159 #define CMU_REG5_PLL_LOCK_RESOLUTION_SET(dst, src) \ argument
160 (((dst) & ~0x0000000e) | (((u32) (src) << 1) & 0x0000000e))
161 #define CMU_REG5_PLL_LFCAP_SET(dst, src) \ argument
162 (((dst) & ~0x00003000) | (((u32) (src) << 12) & 0x00003000))
165 #define CMU_REG6_PLL_VREGTRIM_SET(dst, src) \ argument
166 (((dst) & ~0x00000600) | (((u32) (src) << 9) & 0x00000600))
167 #define CMU_REG6_MAN_PVT_CAL_SET(dst, src) \ argument
168 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
170 #define CMU_REG7_PLL_CALIB_DONE_RD(src) ((0x00004000 & (u32) (src)) >> 14) argument
171 #define CMU_REG7_VCO_CAL_FAIL_RD(src) ((0x00000c00 & (u32) (src)) >> 10) argument
182 #define CMU_REG9_TX_WORD_MODE_CH1_SET(dst, src) \ argument
183 (((dst) & ~0x00000380) | (((u32) (src) << 7) & 0x00000380))
184 #define CMU_REG9_TX_WORD_MODE_CH0_SET(dst, src) \ argument
185 (((dst) & ~0x00000070) | (((u32) (src) << 4) & 0x00000070))
186 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ argument
187 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
188 #define CMU_REG9_VBG_BYPASSB_SET(dst, src) \ argument
189 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
190 #define CMU_REG9_IGEN_BYPASS_SET(dst, src) \ argument
191 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
193 #define CMU_REG10_VREG_REFSEL_SET(dst, src) \ argument
194 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
197 #define CMU_REG12_STATE_DELAY9_SET(dst, src) \ argument
198 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
205 #define CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET(dst, src) \ argument
206 (((dst) & ~0x0000001c) | (((u32) (src) << 2) & 0x0000001c))
207 #define CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET(dst, src) \ argument
208 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
209 #define CMU_REG16_BYPASS_PLL_LOCK_SET(dst, src) \ argument
210 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
212 #define CMU_REG17_PVT_CODE_R2A_SET(dst, src) \ argument
213 (((dst) & ~0x00007f00) | (((u32) (src) << 8) & 0x00007f00))
214 #define CMU_REG17_RESERVED_7_SET(dst, src) \ argument
215 (((dst) & ~0x000000e0) | (((u32) (src) << 5) & 0x000000e0))
226 #define CMU_REG26_FORCE_PLL_LOCK_SET(dst, src) \ argument
227 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
232 #define CMU_REG30_LOCK_COUNT_SET(dst, src) \ argument
233 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
234 #define CMU_REG30_PCIE_MODE_SET(dst, src) \ argument
235 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
239 #define CMU_REG32_PVT_CAL_WAIT_SEL_SET(dst, src) \ argument
240 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
241 #define CMU_REG32_IREF_ADJ_SET(dst, src) \ argument
242 (((dst) & ~0x00000180) | (((u32) (src) << 7) & 0x00000180))
245 #define CMU_REG34_VCO_CAL_VTH_LO_MAX_SET(dst, src) \ argument
246 (((dst) & ~0x0000000f) | (((u32) (src) << 0) & 0x0000000f))
247 #define CMU_REG34_VCO_CAL_VTH_HI_MAX_SET(dst, src) \ argument
248 (((dst) & ~0x00000f00) | (((u32) (src) << 8) & 0x00000f00))
249 #define CMU_REG34_VCO_CAL_VTH_LO_MIN_SET(dst, src) \ argument
250 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
251 #define CMU_REG34_VCO_CAL_VTH_HI_MIN_SET(dst, src) \ argument
252 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
254 #define CMU_REG35_PLL_SSC_MOD_SET(dst, src) \ argument
255 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
257 #define CMU_REG36_PLL_SSC_EN_SET(dst, src) \ argument
258 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
259 #define CMU_REG36_PLL_SSC_VSTEP_SET(dst, src) \ argument
260 (((dst) & ~0x0000ffc0) | (((u32) (src) << 6) & 0x0000ffc0))
261 #define CMU_REG36_PLL_SSC_DSMSEL_SET(dst, src) \ argument
262 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
269 #define RXTX_REG0_CTLE_EQ_HR_SET(dst, src) \ argument
270 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
271 #define RXTX_REG0_CTLE_EQ_QR_SET(dst, src) \ argument
272 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
273 #define RXTX_REG0_CTLE_EQ_FR_SET(dst, src) \ argument
274 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
276 #define RXTX_REG1_RXACVCM_SET(dst, src) \ argument
277 (((dst) & ~0x0000f000) | (((u32) (src) << 12) & 0x0000f000))
278 #define RXTX_REG1_CTLE_EQ_SET(dst, src) \ argument
279 (((dst) & ~0x00000f80) | (((u32) (src) << 7) & 0x00000f80))
280 #define RXTX_REG1_RXVREG1_SET(dst, src) \ argument
281 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
282 #define RXTX_REG1_RXIREF_ADJ_SET(dst, src) \ argument
283 (((dst) & ~0x00000006) | (((u32) (src) << 1) & 0x00000006))
285 #define RXTX_REG2_VTT_ENA_SET(dst, src) \ argument
286 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
287 #define RXTX_REG2_TX_FIFO_ENA_SET(dst, src) \ argument
288 (((dst) & ~0x00000020) | (((u32) (src) << 5) & 0x00000020))
289 #define RXTX_REG2_VTT_SEL_SET(dst, src) \ argument
290 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
293 #define RXTX_REG4_TX_DATA_RATE_SET(dst, src) \ argument
294 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
295 #define RXTX_REG4_TX_WORD_MODE_SET(dst, src) \ argument
296 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
298 #define RXTX_REG5_TX_CN1_SET(dst, src) \ argument
299 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
300 #define RXTX_REG5_TX_CP1_SET(dst, src) \ argument
301 (((dst) & ~0x000007e0) | (((u32) (src) << 5) & 0x000007e0))
302 #define RXTX_REG5_TX_CN2_SET(dst, src) \ argument
303 (((dst) & ~0x0000001f) | (((u32) (src) << 0) & 0x0000001f))
305 #define RXTX_REG6_TXAMP_CNTL_SET(dst, src) \ argument
306 (((dst) & ~0x00000780) | (((u32) (src) << 7) & 0x00000780))
307 #define RXTX_REG6_TXAMP_ENA_SET(dst, src) \ argument
308 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
309 #define RXTX_REG6_RX_BIST_ERRCNT_RD_SET(dst, src) \ argument
310 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
311 #define RXTX_REG6_TX_IDLE_SET(dst, src) \ argument
312 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
313 #define RXTX_REG6_RX_BIST_RESYNC_SET(dst, src) \ argument
314 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
318 #define RXTX_REG7_BIST_ENA_RX_SET(dst, src) \ argument
319 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
320 #define RXTX_REG7_RX_WORD_MODE_SET(dst, src) \ argument
321 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
323 #define RXTX_REG8_CDR_LOOP_ENA_SET(dst, src) \ argument
324 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
325 #define RXTX_REG8_CDR_BYPASS_RXLOS_SET(dst, src) \ argument
326 (((dst) & ~0x00000800) | (((u32) (src) << 11) & 0x00000800))
327 #define RXTX_REG8_SSC_ENABLE_SET(dst, src) \ argument
328 (((dst) & ~0x00000200) | (((u32) (src) << 9) & 0x00000200))
329 #define RXTX_REG8_SD_VREF_SET(dst, src) \ argument
330 (((dst) & ~0x000000f0) | (((u32) (src) << 4) & 0x000000f0))
331 #define RXTX_REG8_SD_DISABLE_SET(dst, src) \ argument
332 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
334 #define RXTX_REG7_RESETB_RXD_SET(dst, src) \ argument
335 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
336 #define RXTX_REG7_RESETB_RXA_SET(dst, src) \ argument
337 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
339 #define RXTX_REG7_LOOP_BACK_ENA_CTLE_SET(dst, src) \ argument
340 (((dst) & ~0x00004000) | (((u32) (src) << 14) & 0x00004000))
342 #define RXTX_REG11_PHASE_ADJUST_LIMIT_SET(dst, src) \ argument
343 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
345 #define RXTX_REG12_LATCH_OFF_ENA_SET(dst, src) \ argument
346 (((dst) & ~0x00002000) | (((u32) (src) << 13) & 0x00002000))
347 #define RXTX_REG12_SUMOS_ENABLE_SET(dst, src) \ argument
348 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
350 #define RXTX_REG12_RX_DET_TERM_ENABLE_SET(dst, src) \ argument
351 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
354 #define RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET(dst, src) \ argument
355 (((dst) & ~0x0000003f) | (((u32) (src) << 0) & 0x0000003f))
356 #define RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET(dst, src) \ argument
357 (((dst) & ~0x00000040) | (((u32) (src) << 6) & 0x00000040))
359 #define RXTX_REG26_PERIOD_ERROR_LATCH_SET(dst, src) \ argument
360 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
361 #define RXTX_REG26_BLWC_ENA_SET(dst, src) \ argument
362 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
364 #define RXTX_REG21_DO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
365 #define RXTX_REG21_XO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
366 #define RXTX_REG21_LATCH_CAL_FAIL_ODD_RD(src) ((0x0000000f & (u32)(src))) argument
368 #define RXTX_REG22_SO_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
369 #define RXTX_REG22_EO_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
370 #define RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD(src) ((0x0000000f & (u32)(src))) argument
372 #define RXTX_REG23_DE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
373 #define RXTX_REG23_XE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
375 #define RXTX_REG24_EE_LATCH_CALOUT_RD(src) ((0x0000fc00 & (u32) (src)) >> 10) argument
376 #define RXTX_REG24_SE_LATCH_CALOUT_RD(src) ((0x000003f0 & (u32) (src)) >> 4) argument
381 #define RXTX_REG38_CUSTOMER_PINMODE_INV_SET(dst, src) \ argument
382 (((dst) & 0x0000fffe) | (((u32) (src) << 1) & 0x0000fffe))
401 #define RXTX_REG61_ISCAN_INBERT_SET(dst, src) \ argument
402 (((dst) & ~0x00000010) | (((u32) (src) << 4) & 0x00000010))
403 #define RXTX_REG61_LOADFREQ_SHIFT_SET(dst, src) \ argument
404 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
405 #define RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET(dst, src) \ argument
406 (((dst) & ~0x000000c0) | (((u32) (src) << 6) & 0x000000c0))
407 #define RXTX_REG61_SPD_SEL_CDR_SET(dst, src) \ argument
408 (((dst) & ~0x00003c00) | (((u32) (src) << 10) & 0x00003c00))
410 #define RXTX_REG62_PERIOD_H1_QLATCH_SET(dst, src) \ argument
411 (((dst) & ~0x00003800) | (((u32) (src) << 11) & 0x00003800))
413 #define RXTX_REG89_MU_TH7_SET(dst, src) \ argument
414 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
415 #define RXTX_REG89_MU_TH8_SET(dst, src) \ argument
416 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
417 #define RXTX_REG89_MU_TH9_SET(dst, src) \ argument
418 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
420 #define RXTX_REG96_MU_FREQ1_SET(dst, src) \ argument
421 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
422 #define RXTX_REG96_MU_FREQ2_SET(dst, src) \ argument
423 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
424 #define RXTX_REG96_MU_FREQ3_SET(dst, src) \ argument
425 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
427 #define RXTX_REG99_MU_PHASE1_SET(dst, src) \ argument
428 (((dst) & ~0x0000f800) | (((u32) (src) << 11) & 0x0000f800))
429 #define RXTX_REG99_MU_PHASE2_SET(dst, src) \ argument
430 (((dst) & ~0x000007c0) | (((u32) (src) << 6) & 0x000007c0))
431 #define RXTX_REG99_MU_PHASE3_SET(dst, src) \ argument
432 (((dst) & ~0x0000003e) | (((u32) (src) << 1) & 0x0000003e))
434 #define RXTX_REG102_FREQLOOP_LIMIT_SET(dst, src) \ argument
435 (((dst) & ~0x00000060) | (((u32) (src) << 5) & 0x00000060))
438 #define RXTX_REG121_SUMOS_CAL_CODE_RD(src) ((0x0000003e & (u32)(src)) >> 0x1) argument
440 #define RXTX_REG125_PQ_REG_SET(dst, src) \ argument
441 (((dst) & ~0x0000fe00) | (((u32) (src) << 9) & 0x0000fe00))
442 #define RXTX_REG125_SIGN_PQ_SET(dst, src) \ argument
443 (((dst) & ~0x00000100) | (((u32) (src) << 8) & 0x00000100))
444 #define RXTX_REG125_SIGN_PQ_2C_SET(dst, src) \ argument
445 (((dst) & ~0x00000080) | (((u32) (src) << 7) & 0x00000080))
446 #define RXTX_REG125_PHZ_MANUALCODE_SET(dst, src) \ argument
447 (((dst) & ~0x0000007c) | (((u32) (src) << 2) & 0x0000007c))
448 #define RXTX_REG125_PHZ_MANUAL_SET(dst, src) \ argument
449 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
453 #define RXTX_REG127_FORCE_SUM_CAL_START_SET(dst, src) \ argument
454 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
455 #define RXTX_REG127_FORCE_LAT_CAL_START_SET(dst, src) \ argument
456 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
457 #define RXTX_REG127_LATCH_MAN_CAL_ENA_SET(dst, src) \ argument
458 (((dst) & ~0x00000008) | (((u32) (src) << 3) & 0x00000008))
459 #define RXTX_REG127_DO_LATCH_MANCAL_SET(dst, src) \ argument
460 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
461 #define RXTX_REG127_XO_LATCH_MANCAL_SET(dst, src) \ argument
462 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
464 #define RXTX_REG128_LATCH_CAL_WAIT_SEL_SET(dst, src) \ argument
465 (((dst) & ~0x0000000c) | (((u32) (src) << 2) & 0x0000000c))
466 #define RXTX_REG128_EO_LATCH_MANCAL_SET(dst, src) \ argument
467 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
468 #define RXTX_REG128_SO_LATCH_MANCAL_SET(dst, src) \ argument
469 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
471 #define RXTX_REG129_DE_LATCH_MANCAL_SET(dst, src) \ argument
472 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
473 #define RXTX_REG129_XE_LATCH_MANCAL_SET(dst, src) \ argument
474 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
476 #define RXTX_REG130_EE_LATCH_MANCAL_SET(dst, src) \ argument
477 (((dst) & ~0x0000fc00) | (((u32) (src) << 10) & 0x0000fc00))
478 #define RXTX_REG130_SE_LATCH_MANCAL_SET(dst, src) \ argument
479 (((dst) & ~0x000003f0) | (((u32) (src) << 4) & 0x000003f0))
481 #define RXTX_REG145_TX_IDLE_SATA_SET(dst, src) \ argument
482 (((dst) & ~0x00000001) | (((u32) (src) << 0) & 0x00000001))
483 #define RXTX_REG145_RXES_ENA_SET(dst, src) \ argument
484 (((dst) & ~0x00000002) | (((u32) (src) << 1) & 0x00000002))
485 #define RXTX_REG145_RXDFE_CONFIG_SET(dst, src) \ argument
486 (((dst) & ~0x0000c000) | (((u32) (src) << 14) & 0x0000c000))
487 #define RXTX_REG145_RXVWES_LATENA_SET(dst, src) \ argument
488 (((dst) & ~0x00000004) | (((u32) (src) << 2) & 0x00000004))
525 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
526 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
527 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
536 struct clk *clk; /* Optional clock */ member
547 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
596 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
607 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
613 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
659 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
668 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
674 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
727 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
737 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
752 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
798 /* Configure the PLL for either 100MHz or 50MHz */ in xgene_phy_sata_cfg_cmu_core()
855 /* Configure lane for 20-bits */ in xgene_phy_sata_cfg_cmu_core()
959 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
960 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
972 /* Configure Tx for 20-bits */ in xgene_phy_sata_cfg_lanes()
984 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ in xgene_phy_sata_cfg_lanes()
987 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
988 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
990 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
991 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
993 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
994 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1000 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1008 /* Configure Rx for 20-bits */ in xgene_phy_sata_cfg_lanes()
1046 /* Set Eye Monitor counter width to 12-bit */ in xgene_phy_sata_cfg_lanes()
1095 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1096 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1098 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1099 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1138 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1187 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN in xgene_phy_cal_rdy_chk()
1217 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1220 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1223 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1225 return -1; in xgene_phy_cal_rdy_chk()
1227 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1230 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1240 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1255 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1260 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1274 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1277 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1295 /* Set Rx/Tx 20-bit */ in xgene_phy_hw_init_sata()
1308 } while (--i > 0); in xgene_phy_hw_init_sata()
1311 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1322 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1324 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1329 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1330 ctx->mode); in xgene_phy_hw_initialize()
1331 return -ENODEV; in xgene_phy_hw_initialize()
1340 * Calibrate the receiver signal path offset in two steps - summar and
1437 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1440 /* Enable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1450 * Calibrate the receiver signal path offset in two steps - summar in xgene_phy_gen_avg_val()
1493 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1494 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1497 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1500 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1503 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1545 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1546 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1551 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1556 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1562 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1566 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1569 /* Disable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1587 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1592 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1594 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1595 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1596 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1603 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1617 if (args->args_count <= 0) in xgene_phy_xlate()
1618 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1619 if (args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1620 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1622 ctx->mode = args->args[0]; in xgene_phy_xlate()
1623 return ctx->phy; in xgene_phy_xlate()
1633 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, in xgene_phy_get_param()
1658 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1660 return -ENOMEM; in xgene_phy_probe()
1662 ctx->dev = &pdev->dev; in xgene_phy_probe()
1664 ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); in xgene_phy_probe()
1665 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1666 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1669 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1672 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", in xgene_phy_probe()
1673 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1674 xgene_phy_get_param(pdev, "apm,tx-eye-direction", in xgene_phy_probe()
1675 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1676 xgene_phy_get_param(pdev, "apm,tx-boost-gain", in xgene_phy_probe()
1677 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1678 xgene_phy_get_param(pdev, "apm,tx-amplitude", in xgene_phy_probe()
1679 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1680 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", in xgene_phy_probe()
1681 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1682 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", in xgene_phy_probe()
1683 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1684 xgene_phy_get_param(pdev, "apm,tx-post-cursor", in xgene_phy_probe()
1685 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1686 xgene_phy_get_param(pdev, "apm,tx-speed", in xgene_phy_probe()
1687 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1689 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1693 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1694 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1695 dev_dbg(&pdev->dev, "Failed to create PHY\n"); in xgene_phy_probe()
1696 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1698 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1700 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()
1705 {.compatible = "apm,xgene-phy",},
1713 .name = "xgene-phy",
1719 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");