| /Linux-v5.10/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
57 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
[all …]
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| /Linux-v5.10/drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
[all …]
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| D | radeon_combios.c | 739 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
766 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
767 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
768 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
769 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
772 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
773 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
776 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
777 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
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| D | radeon_atombios.c | 1138 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1191 spll->reference_freq = in radeon_atom_get_clock_info()
1194 spll->reference_freq = in radeon_atom_get_clock_info()
1196 spll->reference_div = 0; in radeon_atom_get_clock_info()
1198 spll->pll_out_min = in radeon_atom_get_clock_info()
1200 spll->pll_out_max = in radeon_atom_get_clock_info()
1204 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1206 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1208 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1211 spll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
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| D | rv6xx_dpm.c | 163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
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| D | rv740_dpm.c | 131 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
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| D | rs780_dpm.c | 992 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1014 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
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| D | rv730_dpm.c | 51 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
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| /Linux-v5.10/drivers/clk/imx/ |
| D | clk-imx31.c | 34 static const char *mcu_main_sel[] = { "spll", "mpll", };
36 static const char *csi_sel[] = { "upll", "spll", };
37 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
40 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
70 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
98 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); in _mx31_clocks_init()
118 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); in _mx31_clocks_init()
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| D | clk-imx7ulp.c | 24 static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
95 hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4("spll", "spll_pre_div", base + 0x600); in imx7ulp_clk_scg1_init()
103 /* SPLL PFDs */ in imx7ulp_clk_scg1_init()
104 hws[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0); in imx7ulp_clk_scg1_init()
105 hws[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1); in imx7ulp_clk_scg1_init()
106 hws[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2); in imx7ulp_clk_scg1_init()
107 hws[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3); in imx7ulp_clk_scg1_init()
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| D | clk-imx27.c | 34 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
40 "ckih_gate", "mpll", "spll", "cpu_div",
76 clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); in _mx27_clocks_init()
77 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in _mx27_clocks_init()
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| D | clk-imx1.c | 49 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in mx1_clocks_init_dt()
50 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx1_clocks_init_dt()
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| /Linux-v5.10/drivers/clk/microchip/ |
| D | clk-core.c | 75 /* SoC specific clock needed during SPLL clock rate switch */
628 pr_warn("spll: no match found\n"); in spll_calc_mult_div()
689 * We can't change SPLL counters when it is in-active use in spll_clk_set_rate()
725 /* SPLL clock operation */
735 struct pic32_sys_pll *spll; in pic32_spll_clk_register() local
738 spll = devm_kzalloc(core->dev, sizeof(*spll), GFP_KERNEL); in pic32_spll_clk_register()
739 if (!spll) in pic32_spll_clk_register()
742 spll->core = core; in pic32_spll_clk_register()
743 spll->hw.init = &data->init_data; in pic32_spll_clk_register()
744 spll->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_spll_clk_register()
[all …]
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| D | clk-pic32mzda.c | 23 /* SPLL fields */
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| /Linux-v5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atomfirmware.c | 380 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atomfirmware_get_clock_info() local
418 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
420 spll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
421 spll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
422 spll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
423 spll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
424 spll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
425 spll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
426 spll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
427 spll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
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| D | amdgpu_atombios.c | 570 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
616 spll->reference_freq = in amdgpu_atombios_get_clock_info()
618 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
620 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
622 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
626 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
627 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
629 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
631 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
634 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
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| /Linux-v5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
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| D | nv50.c | 467 /* shader: tie to nvclk if possible, otherwise use spll. have to be in nv50_clk_calc()
474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
483 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
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| D | mcp77.c | 240 /* sclk: nvpll + divisor, href or spll */ in mcp77_clk_calc()
275 nvkm_debug(subdev, " spll: %08x %08x %08x\n", in mcp77_clk_calc()
288 nvkm_debug(subdev, "shader: spll\n"); in mcp77_clk_calc()
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| /Linux-v5.10/arch/mips/pic32/pic32mzda/ |
| D | early_clk.c | 18 #define SPLL 1 macro
71 case SPLL: in pic32_get_sysclk()
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| /Linux-v5.10/arch/arm/mach-imx/ |
| D | pm-imx27.c | 29 /* Clear MPEN and SPEN to disable MPLL/SPLL */ in mx27_suspend_enter()
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | imx31-clock.yaml | 23 spll 4
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| /Linux-v5.10/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 78 * @DPLL_ID_SPLL: HSW and BDW SPLL
177 u32 spll; member
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| D | intel_dpll_mgr.c | 566 intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
641 hw_state->spll = val; in hsw_ddi_spll_get_hw_state()
997 crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | in hsw_ddi_spll_get_dpll()
1009 switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) { in hsw_ddi_spll_get_freq()
1020 drm_WARN(&i915->drm, 1, "bad spll freq\n"); in hsw_ddi_spll_get_freq()
1071 drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", in hsw_dump_hw_state()
1072 hw_state->wrpll, hw_state->spll); in hsw_dump_hw_state()
1116 { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 },
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| /Linux-v5.10/drivers/video/fbdev/aty/ |
| D | radeon_pm.c | 1478 /* Switch SPLL to PCI source */ in radeon_pm_start_mclk_sclk()
1482 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */ in radeon_pm_start_mclk_sclk()
1489 /* Set SPLL feedback divider */ in radeon_pm_start_mclk_sclk()
1494 /* Power up SPLL */ in radeon_pm_start_mclk_sclk()
1501 /* Release SPLL reset */ in radeon_pm_start_mclk_sclk()
1654 /* Reconfigure SPLL charge pump, VCO gain, duty cycle, in radeon_pm_restore_pixel_pll()
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