Lines Matching full:spll
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
57 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 8), \
61 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 12), \
65 UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
69 UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
73 UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
89 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
105 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
106 UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
131 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
132 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
133 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
143 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
147 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
148 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
162 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1), /* 2400 MHz */
163 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
164 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
165 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
188 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
190 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
191 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
192 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
207 UNIPHIER_CLK_DIV3("spll", 3, 4, 8),
208 /* Note: both gear1 and gear4 are spll/4. This is not a bug. */
210 "cpll/2", "spll/4", "cpll/3", "spll/3",
211 "spll/4", "spll/8", "cpll/4", "cpll/8"),
213 "mpll/2", "spll/4", "mpll/3", "spll/3",
214 "spll/4", "spll/8", "mpll/4", "mpll/8"),
222 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
225 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
226 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
227 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
252 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
255 "cpll/2", "spll/2", "cpll/3", "spll/3",
256 "spll/4", "spll/8", "cpll/4", "cpll/8"),
258 "cpll/2", "spll/2", "cpll/3", "spll/3",
259 "spll/4", "spll/8", "cpll/4", "cpll/8"),
261 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
262 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),
268 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 80, 1), /* 2000 MHz */
270 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
271 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
272 UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
293 UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
296 "cpll/2", "spll/2", "cpll/3", "spll/3",
297 "spll/4", "spll/8", "cpll/4", "cpll/8"),
299 "s2pll/2", "spll/2", "s2pll/3", "spll/3",
300 "spll/4", "spll/8", "s2pll/4", "s2pll/8"),