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/Linux-v5.4/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
[all …]
Dallwinner,sun6i-a31-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <maxime.ripard@bootlin.com>
17 "#address-cells": true
18 "#size-cells": true
[all …]
Dallwinner,sun4i-a10-spi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 SPI Controller Device Tree Bindings
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <maxime.ripard@bootlin.com>
17 "#address-cells": true
18 "#size-cells": true
[all …]
Dspi-stm32-qspi.txt4 - compatible: should be "st,stm32f469-qspi"
5 - reg: the first contains the register location and length.
7 - reg-names: should contain the reg names "qspi" "qspi_mm"
8 - interrupts: should contain the interrupt for the device
9 - clocks: the phandle of the clock needed by the QSPI controller
10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
13 - resets: must contain the phandle to the reset controller.
15 A spi flash (NOR/NAND) must be a child of spi node and could have some
16 properties. Also see jedec,spi-nor.txt.
19 - reg: chip-Select number (QSPI controller may connect 2 flashes)
[all …]
Dqcom,spi-qcom-qspi.txt3 The QSPI controller allows SPI protocol communication in single, dual, or quad
7 - compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as
8 "qcom,sdm845-qspi", "qcom,qspi-v1"
9 - reg: Should contain the base register location and length.
10 - interrupts: Interrupt number used by the controller.
11 - clocks: Should contain the core and AHB clock.
12 - clock-names: Should be "core" for core clock and "iface" for AHB clock.
14 SPI slave nodes must be children of the SPI master node and can contain
15 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
19 qspi: spi@88df000 {
[all …]
Dspi-mxic.txt1 Macronix SPI controller Device Tree Bindings
2 --------------------------------------------
5 - compatible: should be "mxicy,mx25f0a-spi"
6 - #address-cells: should be 1
7 - #size-cells: should be 0
8 - reg: should contain 2 entries, one for the registers and one for the direct
10 - reg-names: should contain "regs" and "dirmap"
11 - interrupts: interrupt line connected to the SPI controller
12 - clock-names: should contain "ps_clk", "send_clk" and "send_dly_clk"
13 - clocks: should contain 3 entries for the "ps_clk", "send_clk" and
[all …]
/Linux-v5.4/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
21 stdout-path = "serial0:115200n8";
24 sb_3v3: regulator-sb3v3 {
25 compatible = "regulator-fixed";
26 regulator-name = "MC34717-3.3VSB";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 mmc-hs200-1_8v;
19 #address-cells = <2>;
20 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "cfi-flash";
30 bank-width = <2>;
31 device-width = <1>;
35 compatible = "fsl,ifc-nand";
[all …]
Dfsl-ls1046a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 stdout-path = "serial0:115200n8";
39 mmc-hs200-1_8v;
40 sd-uhs-sdr104;
41 sd-uhs-sdr50;
42 sd-uhs-sdr25;
[all …]
Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
31 stdout-path = "serial0:115200n8";
36 bus-num = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "n25q128a11", "jedec,spi-nor";
[all …]
Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
30 stdout-path = "serial0:115200n8";
43 #address-cells = <2>;
44 #size-cells = <1>;
52 compatible = "cfi-flash";
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dimx6sx-sdb.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
12 clock-frequency = <100000>;
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_i2c1>;
23 regulator-min-microvolt = <300000>;
24 regulator-max-microvolt = <1875000>;
25 regulator-boot-on;
26 regulator-always-on;
27 regulator-ramp-delay = <6250>;
[all …]
Dimx6sx-sdb-reva.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dtsi"
12 clock-frequency = <100000>;
13 pinctrl-names = "default";
14 pinctrl-0 = <&pinctrl_i2c1>;
23 regulator-min-microvolt = <300000>;
24 regulator-max-microvolt = <1875000>;
25 regulator-boot-on;
26 regulator-always-on;
27 regulator-ramp-delay = <6250>;
[all …]
Dr8a7743-iwg20m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1M-20M Qseven SOM
9 #include <dt-bindings/gpio/gpio.h>
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 regulator-boot-on;
35 clock-frequency = <20000000>;
[all …]
Dr8a7744-iwg20m.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/gpio/gpio.h>
20 compatible = "regulator-fixed";
21 regulator-name = "3P3V";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 regulator-always-on;
25 regulator-boot-on;
30 clock-frequency = <20000000>;
47 power-source = <3300>;
[all …]
Dr8a7745-iwg22m.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM
9 #include <dt-bindings/gpio/gpio.h>
20 compatible = "regulator-fixed";
21 regulator-name = "3P3V";
22 regulator-min-microvolt = <3300000>;
23 regulator-max-microvolt = <3300000>;
24 regulator-always-on;
25 regulator-boot-on;
34 clock-frequency = <20000000>;
[all …]
Dat91-sama5d27_som1.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
10 #include "sama5d2-pinfunc.h"
14 compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
18 clock-frequency = <32768>;
22 clock-frequency = <24000000>;
28 qspi1: spi@f0024000 {
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_qspi1_default>;
33 compatible = "jedec,spi-nor";
[all …]
Datlas6.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
[all …]
Dimx6ul-kontron-n6310-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/gpio/gpio.h>
13 compatible = "kontron,imx6ul-n6310-som", "fsl,imx6ul";
22 cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_ecspi2>;
27 spi-flash@0 {
28 compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
29 spi-max-frequency = <50000000>;
35 pinctrl-names = "default";
[all …]
Ddra7-evm-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clk/ti-dra7-atl.h>
8 #include <dt-bindings/input/input.h>
12 stdout-path = &uart1;
16 compatible = "linux,extcon-usb-gpio";
17 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
21 compatible = "linux,extcon-usb-gpio";
22 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
[all …]
Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
33 #size-cells = <0>;
[all …]
/Linux-v5.4/arch/riscv/boot/dts/sifive/
Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
10 #address-cells = <2>;
11 #size-cells = <2>;
13 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
16 stdout-path = "serial0";
20 timebase-frequency = <RTCCLK_FREQ>;
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
[all …]
/Linux-v5.4/arch/arm64/boot/dts/marvell/
Darmada-3720-uDPU.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include "armada-372x.dtsi"
22 stdout-path = "serial0:115200n8";
31 pinctrl-names = "default";
32 compatible = "gpio-leds";
65 sfp_eth0: sfp-eth0 {
67 i2c-bus = <&i2c0>;
[all …]
/Linux-v5.4/arch/powerpc/boot/dts/
Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
[all …]
/Linux-v5.4/drivers/spi/
Dspi-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Broadcom BCM2835 SPI Controllers
10 * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
11 * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
18 #include <linux/dma-mapping.h>
32 #include <linux/spi/spi.h>
34 /* SPI register offsets */
75 #define DRV_NAME "spi-bcm2835"
84 * struct bcm2835_spi - BCM2835 SPI controller
87 * @irq: interrupt, signals TX FIFO empty or RX FIFO ¾ full
[all …]

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