Lines Matching +full:spi +full:- +full:tx +full:- +full:bus +full:- +full:width
3 The QSPI controller allows SPI protocol communication in single, dual, or quad
7 - compatible: An SoC specific identifier followed by "qcom,qspi-v1", such as
8 "qcom,sdm845-qspi", "qcom,qspi-v1"
9 - reg: Should contain the base register location and length.
10 - interrupts: Interrupt number used by the controller.
11 - clocks: Should contain the core and AHB clock.
12 - clock-names: Should be "core" for core clock and "iface" for AHB clock.
14 SPI slave nodes must be children of the SPI master node and can contain
15 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
19 qspi: spi@88df000 {
20 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 clock-names = "iface", "core";
30 compatible = "jedec,spi-nor";
32 spi-max-frequency = <25000000>;
33 spi-tx-bus-width = <2>;
34 spi-rx-bus-width = <2>;