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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
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Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
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Dspi-bcm63xx-hsspi.txt1 Binding for Broadcom BCM6328 High Speed SPI controller
4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
16 Child nodes as per the generic SPI binding.
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Drenesas,sh-msiof.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/renesas,sh-msiof.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas MSIOF SPI controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: spi-controller.yaml#
18 - items:
19 - const: renesas,msiof-sh73a0 # SH-Mobile AG5
20 - const: renesas,sh-mobile-msiof # generic SH-Mobile compatible
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/Linux-v6.1/Documentation/devicetree/bindings/rtc/
Depson,rx6110.txt4 The Epson RX6110 can be used with SPI or I2C busses. The kind of
8 --------
11 - compatible: should be: "epson,rx6110"
12 - reg : the I2C address of the device for I2C
21 SPI mode
22 --------
25 - compatible: should be: "epson,rx6110"
26 - reg: chip select number
27 - spi-cs-high: RX6110 needs chipselect high
28 - spi-cpha: RX6110 works with SPI shifted clock phase
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Dnxp,rtc-2123.txt1 NXP PCF2123 SPI Real Time Clock
4 - compatible: should be: "nxp,pcf2123"
6 - reg: should be the SPI slave chipselect address
9 - spi-cs-high: PCF2123 needs chipselect high
16 spi-cs-high;
Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
12 - compatible : Should be "maxim,ds1302"
14 Required SPI properties:
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
32 spi@901c {
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/Linux-v6.1/arch/arm64/boot/dts/qcom/
Dsc7280-idp-ec-h1.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
11 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
12 cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
15 compatible = "google,cros-ec-spi";
17 interrupt-parent = <&tlmm>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&ap_ec_int_l>;
21 spi-max-frequency = <3000000>;
24 compatible = "google,cros-ec-pwm";
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/Linux-v6.1/Documentation/devicetree/bindings/gpio/
Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
4 Cell spi controller through its system registers, which otherwise remains under
7 desired by some of the device protocols above spi which expect (multiple)
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
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/Linux-v6.1/drivers/gpio/
Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
24 #include "gpiolib-of.h"
27 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
33 * established "cs-gpios" for chip selects but instead rely on
35 * the counting of "cs-gpios" to count "gpios" transparent to the
40 struct device_node *np = dev->of_node; in of_gpio_spi_cs_get_count()
44 if (!con_id || strcmp(con_id, "cs")) in of_gpio_spi_cs_get_count()
46 if (!of_device_is_compatible(np, "fsl,spi") && in of_gpio_spi_cs_get_count()
48 !of_device_is_compatible(np, "ibm,ppc4xx-spi")) in of_gpio_spi_cs_get_count()
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Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPEAr platform SPI chipselect abstraction over gpiolib
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
22 * through system registers. This register lies outside spi (pl022)
25 * It provides control for spi chip select lines so that any chipselect
31 * struct spear_spics - represents spi chip select control
35 * @cs_value_bit: bit to program high or low chipselect
38 * @use_count: use count of a spi controller cs lines
57 return -ENXIO; in spics_get_value()
66 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
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/Linux-v6.1/drivers/spi/
Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
20 * during SPI transfers by setting max_speed_hz via the device tree.
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
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Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * polling/bitbanging SPI master controller driver utilities
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
21 /*----------------------------------------------------------------------*/
24 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
25 * Use this for GPIO or shift-register level hardware APIs.
27 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
29 * used, though maybe they're called from controller-aware code.
31 * chipselect() and friends may use spi_device->controller_data and
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Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
98 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
114 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, in bcm63xx_hsspi_set_cs() argument
119 mutex_lock(&bs->bus_mutex); in bcm63xx_hsspi_set_cs()
120 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_cs()
122 reg &= ~BIT(cs); in bcm63xx_hsspi_set_cs()
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Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
14 #include <linux/spi/spi.h>
18 #define DRIVER_NAME "rockchip-spi"
25 /* SPI register offsets */
62 /* ss_n be high for half sclk_out cycles */
64 /* ss_n be high for one sclk_out cycle */
154 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
163 /* 2 for native cs, 2 for cs-gpio */
[all …]
Dspi-dln2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
13 #include <linux/spi/spi.h>
20 /* SPI commands */
88 * needed because all SPI communication is serialized by the SPI core.
95 u8 cs; member
99 * Enable/Disable SPI module. The disable command will wait for transfers to
111 tx.port = dln2->port; in dln2_spi_enable()
115 len -= sizeof(tx.wait_for_completion); in dln2_spi_enable()
121 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); in dln2_spi_enable()
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Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SPI master driver using generic bitbanged GPIO
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
17 #include <linux/spi/spi_gpio.h>
21 * This bitbanging SPI master driver should help make systems usable
22 * when a native hardware SPI engine is not available, perhaps because
26 * platform_device->driver_data ... points to spi_gpio
28 * spi->controller_state ... reserved for bitbang framework code
30 * spi->master->dev.driver_data ... points to spi_gpio->bitbang
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Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Designware SPI core controller driver (refer pxa2xx_spi.c)
9 #include <linux/dma-mapping.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
21 #include "spi-dw.h"
64 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
65 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
66 if (!dws->debugfs) in dw_spi_debugfs_init()
67 return -ENOMEM; in dw_spi_debugfs_init()
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/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Dmotorola-cpcap.txt4 - compatible : One or both of "motorola,cpcap" or "ste,6556002"
5 - reg : SPI chip select
6 - interrupts : The interrupt line the device is connected to
7 - interrupt-controller : Marks the device node as an interrupt controller
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2
9 - #address-cells : Child device offset number of cells, should be 1
10 - #size-cells : Child device size number of cells, should be 0
11 - spi-max-frequency : Typically set to 3000000
12 - spi-cs-high : SPI chip select direction
16 The sub-functions of CPCAP get their own node with their own compatible values,
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/Linux-v6.1/include/linux/dma/
Dqcom-gpi-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum spi_transfer_cmd - spi transfer commands
19 * struct gpi_spi_config - spi config for peripheral
21 * @loopback_en: spi loopback enable when set
25 * @word_len: spi word length
28 * @cmd: spi cmd
29 * @fragmentation: keep CS asserted at end of sequence
30 * @cs: chip select toggle
42 u8 cs; member
55 * struct gpi_i2c_config - i2c config for peripheral
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/Linux-v6.1/arch/riscv/boot/dts/canaan/
Dsipeed_maix_bit.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm",
18 "canaan,kendryte-k210";
22 stdout-path = "serial0:115200n8";
25 gpio-leds {
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/Linux-v6.1/arch/arm64/boot/dts/xilinx/
Dzynqmp-zc1751-xm016-dc2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 model = "ZynqMP zc1751-xm016-dc2 RevA";
19 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
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/Linux-v6.1/drivers/platform/chrome/
Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
14 #include <linux/spi/spi.h>
24 * about 400-500us for the EC to respond there is not a lot of
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
50 * for this, clocking in at 2-3ms.
55 * Time between raising the SPI chip select (for the end of a
64 * struct cros_ec_spi - information about a SPI-connected EC
66 * @spi: SPI device we are connected to
69 * is sent when we want to turn on CS at the start of a transaction.
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/Linux-v6.1/arch/powerpc/boot/dts/
Dac14xx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
23 uart1(cts), lcd-spi(cs1), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
41 ac97-1(sysclko)
44 mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
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