Searched +full:sparx5 +full:- +full:dpll (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Microchip Sparx5 DPLL Clock10 - Lars Povlsen <lars.povlsen@microchip.com>13 The Sparx5 DPLL clock controller generates and supplies clock to18 const: microchip,sparx5-dpll26 '#clock-cells':30 - compatible[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/gpio/gpio.h>7 #include <dt-bindings/interrupt-controller/arm-gic.h>8 #include <dt-bindings/clock/microchip,sparx5.h>11 compatible = "microchip,sparx5";12 interrupt-parent = <&gic>;13 #address-cells = <2>;14 #size-cells = <1>;23 stdout-path = "serial0:115200n8";27 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * Microchip Sparx5 SoC Clock driver.12 #include <linux/clk-provider.h>17 #include <dt-bindings/clock/microchip,sparx5.h>61 unsigned long rate = parent_rate / conf->div; in s5_calc_freq()63 if (conf->rot_ena) { in s5_calc_freq()64 int sign = conf->rot_dir ? -1 : 1; in s5_calc_freq()65 int divt = sel_rates[conf->rot_sel] * (1 + conf->pre_div); in s5_calc_freq()85 conf->div = div; in s5_search_fractional()86 conf->rot_ena = 1; /* Fractional rate */ in s5_search_fractional()[all …]
