Lines Matching +full:sparx5 +full:- +full:dpll
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <2>;
28 #size-cells = <0>;
29 cpu-map {
40 compatible = "arm,cortex-a53";
43 enable-method = "psci";
44 next-level-cache = <&L2_0>;
47 compatible = "arm,cortex-a53";
50 enable-method = "psci";
51 next-level-cache = <&L2_0>;
53 L2_0: l2-cache0 {
58 arm-pmu {
59 compatible = "arm,cortex-a53-pmu";
61 interrupt-affinity = <&cpu0>, <&cpu1>;
65 compatible = "arm,psci-0.2";
70 compatible = "arm,armv8-timer";
77 lcpll_clk: lcpll-clk {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <2500000000>;
83 clks: clock-controller@61110000c {
84 compatible = "microchip,sparx5-dpll";
85 #clock-cells = <1>;
90 ahb_clk: ahb-clk {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 clock-frequency = <250000000>;
96 sys_clk: sys-clk {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <625000000>;
103 compatible = "simple-bus";
104 #address-cells = <2>;
105 #size-cells = <1>;
108 gic: interrupt-controller@600300000 {
109 compatible = "arm,gic-v3";
110 #interrupt-cells = <3>;
111 #address-cells = <2>;
112 #size-cells = <2>;
113 interrupt-controller;
123 compatible = "microchip,sparx5-cpu-syscon", "syscon",
124 "simple-mfd";
126 mux: mux-controller {
127 compatible = "mmio-mux";
128 #mux-control-cells = <0>;
131 * SPI: value 9 - (SIMC,SIBM) = 0b1001
132 * SPI2: value 6 - (SIBM,SIMC) = 0b0110
134 mux-reg-masks = <0x88 0xf0>;
138 reset: reset-controller@611010008 {
139 compatible = "microchip,sparx5-switch-reset";
141 reg-names = "gcb";
142 #reset-cells = <1>;
143 cpu-syscon = <&cpu_ctrl>;
147 pinctrl-0 = <&uart_pins>;
148 pinctrl-names = "default";
152 reg-io-width = <4>;
153 reg-shift = <2>;
160 pinctrl-0 = <&uart2_pins>;
161 pinctrl-names = "default";
165 reg-io-width = <4>;
166 reg-shift = <2>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "microchip,sparx5-spi";
177 num-cs = <16>;
178 reg-io-width = <4>;
179 reg-shift = <2>;
186 compatible = "snps,dw-apb-timer";
189 clock-names = "timer";
194 compatible = "microchip,dw-sparx5-sdhci";
197 pinctrl-0 = <&emmc_pins>;
198 pinctrl-names = "default";
200 clock-names = "core";
201 assigned-clocks = <&clks CLK_ID_AUX1>;
202 assigned-clock-rates = <800000000>;
204 bus-width = <8>;
208 compatible = "microchip,sparx5-pinctrl";
210 gpio-controller;
211 #gpio-cells = <2>;
212 gpio-ranges = <&gpio 0 0 64>;
213 interrupt-controller;
215 #interrupt-cells = <2>;
217 cs1_pins: cs1-pins {
222 cs2_pins: cs2-pins {
227 cs3_pins: cs3-pins {
232 si2_pins: si2-pins {
237 sgpio0_pins: sgpio-pins {
242 sgpio1_pins: sgpio1-pins {
247 sgpio2_pins: sgpio2-pins {
253 uart_pins: uart-pins {
258 uart2_pins: uart2-pins {
263 i2c_pins: i2c-pins {
268 i2c2_pins: i2c2-pins {
273 emmc_pins: emmc-pins {
282 miim1_pins: miim1-pins {
287 miim2_pins: miim2-pins {
292 miim3_pins: miim3-pins {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "microchip,sparx5-sgpio";
304 pinctrl-0 = <&sgpio0_pins>;
305 pinctrl-names = "default";
307 reset-names = "switch";
310 compatible = "microchip,sparx5-sgpio-bank";
312 gpio-controller;
313 #gpio-cells = <3>;
316 interrupt-controller;
317 #interrupt-cells = <3>;
320 compatible = "microchip,sparx5-sgpio-bank";
322 gpio-controller;
323 #gpio-cells = <3>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 compatible = "microchip,sparx5-sgpio";
334 pinctrl-0 = <&sgpio1_pins>;
335 pinctrl-names = "default";
337 reset-names = "switch";
340 compatible = "microchip,sparx5-sgpio-bank";
342 gpio-controller;
343 #gpio-cells = <3>;
346 interrupt-controller;
347 #interrupt-cells = <3>;
350 compatible = "microchip,sparx5-sgpio-bank";
352 gpio-controller;
353 #gpio-cells = <3>;
359 #address-cells = <1>;
360 #size-cells = <0>;
361 compatible = "microchip,sparx5-sgpio";
364 pinctrl-0 = <&sgpio2_pins>;
365 pinctrl-names = "default";
367 reset-names = "switch";
371 compatible = "microchip,sparx5-sgpio-bank";
372 gpio-controller;
373 #gpio-cells = <3>;
376 interrupt-controller;
377 #interrupt-cells = <3>;
380 compatible = "microchip,sparx5-sgpio-bank";
382 gpio-controller;
383 #gpio-cells = <3>;
389 compatible = "snps,designware-i2c";
391 pinctrl-0 = <&i2c_pins>;
392 pinctrl-names = "default";
394 #address-cells = <1>;
395 #size-cells = <0>;
397 i2c-sda-hold-time-ns = <300>;
398 clock-frequency = <100000>;
403 compatible = "snps,designware-i2c";
405 pinctrl-0 = <&i2c2_pins>;
406 pinctrl-names = "default";
408 #address-cells = <1>;
409 #size-cells = <0>;
411 i2c-sda-hold-time-ns = <300>;
412 clock-frequency = <100000>;
417 compatible = "microchip,sparx5-temp";
419 #thermal-sensor-cells = <0>;
424 compatible = "mscc,ocelot-miim";
426 #address-cells = <1>;
427 #size-cells = <0>;
432 compatible = "mscc,ocelot-miim";
434 pinctrl-0 = <&miim1_pins>;
435 pinctrl-names = "default";
436 #address-cells = <1>;
437 #size-cells = <0>;
442 compatible = "mscc,ocelot-miim";
444 pinctrl-0 = <&miim2_pins>;
445 pinctrl-names = "default";
446 #address-cells = <1>;
447 #size-cells = <0>;
452 compatible = "mscc,ocelot-miim";
454 pinctrl-0 = <&miim3_pins>;
455 pinctrl-names = "default";
456 #address-cells = <1>;
457 #size-cells = <0>;
462 compatible = "microchip,sparx5-serdes";
463 #phy-cells = <1>;
469 compatible = "microchip,sparx5-switch";
473 reg-names = "cpu", "dev", "gcb";
474 interrupt-names = "xtr", "fdma", "ptp";
479 reset-names = "switch";