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/Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/
Dmediatek,smi-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
16 MediaTek SMI have two generations of HW architecture, here is the list
21 There's slight differences between the two SMI, for generation 2, the
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
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/Linux-v5.15/drivers/memory/
Dmtk-smi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
16 #include <soc/mediatek/smi.h>
17 #include <dt-bindings/memory/mt2701-larb-port.h>
18 #include <dt-bindings/memory/mtk-memory-port.h>
37 * or non-security.
52 /* SMI COMMON */
89 struct mtk_smi smi; member
98 static int mtk_smi_clk_enable(const struct mtk_smi *smi) in mtk_smi_clk_enable() argument
102 ret = clk_prepare_enable(smi->clk_apb); in mtk_smi_clk_enable()
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/Linux-v5.15/Documentation/devicetree/bindings/iommu/
Dmediatek,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
33 SMI Common(Smart Multimedia Interface Common)
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/Linux-v5.15/arch/arm/boot/dts/
Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/Linux-v5.15/arch/arm/mach-omap2/
Dsleep34xx.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Karthik Dasu <karthik-dp@ti.com>
9 * Richard Woodruff <r-woodruff2@ti.com>
57 * with non-Thumb-2-capable firmware.
86 .arch armv7-a
89 stmfd sp!, {r4 - r11, lr} @ save registers on stack
98 smc #1 @ call SMI monitor (smi #1)
103 ldmfd sp!, {r4 - r11, pc}
115 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
121 * - only the minimum set of functions gets copied to internal SRAM at boot
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/Linux-v5.15/arch/arm64/boot/dts/mediatek/
Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
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Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
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Dmt8183.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/gce/mt8183-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8183-larb-port.h>
13 #include <dt-bindings/power/mt8183-power.h>
14 #include <dt-bindings/reset-controller/mt8183-resets.h>
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/thermal/thermal.h>
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Dmt8173.dtsi14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include <dt-bindings/gce/mt8173-gce.h>
22 #include <dt-bindings/thermal/thermal.h>
23 #include "mt8173-pinfunc.h"
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/Linux-v5.15/Documentation/devicetree/bindings/pinctrl/
Dmarvell,armada-98dx3236-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
46 mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1)
Dmarvell,armada-37xx-pinctrl.txt12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
17 common pinctrl bindings used by client devices, including the meaning
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
33 - pins 20-24
34 - functions jtag, gpio
37 - pins 8-10
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Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
23 mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio)
35 mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
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/Linux-v5.15/drivers/net/dsa/
Drtl8366rb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
23 #include "realtek-smi-core.h"
315 * struct rtl8366rb - RTL8366RB-specific data
316 * @max_mtu: per-port max MTU setting
358 static int rtl8366rb_get_mib_counter(struct realtek_smi *smi, in rtl8366rb_get_mib_counter() argument
369 mib->offset; in rtl8366rb_get_mib_counter()
374 ret = regmap_write(smi->map, addr, 0); /* Write whatever */ in rtl8366rb_get_mib_counter()
379 ret = regmap_read(smi->map, RTL8366RB_MIB_CTRL_REG, &val); in rtl8366rb_get_mib_counter()
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/Linux-v5.15/drivers/mmc/host/
Dcavium.c9 * Copyright (C) 2012-2017 Cavium Inc.
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
46 * being used. However, non-MMC devices like SD use command and
128 cr = cvm_mmc_cr_types + (cmd->opcode & 0x3f); in cvm_mmc_get_cr_mods()
129 hardware_ctype = cr->ctype; in cvm_mmc_get_cr_mods()
130 hardware_rtype = cr->rtype; in cvm_mmc_get_cr_mods()
131 if (cmd->opcode == MMC_GEN_CMD) in cvm_mmc_get_cr_mods()
132 hardware_ctype = (cmd->arg & 1) ? 1 : 2; in cvm_mmc_get_cr_mods()
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Dcavium.h8 * Copyright (C) 2012-2017 Cavium Inc.
26 #define MIO_EMM_DMA_FIFO_CFG(x) (0x00 + x->reg_off_dma)
27 #define MIO_EMM_DMA_FIFO_ADR(x) (0x10 + x->reg_off_dma)
28 #define MIO_EMM_DMA_FIFO_CMD(x) (0x18 + x->reg_off_dma)
29 #define MIO_EMM_DMA_CFG(x) (0x20 + x->reg_off_dma)
30 #define MIO_EMM_DMA_ADR(x) (0x28 + x->reg_off_dma)
31 #define MIO_EMM_DMA_INT(x) (0x30 + x->reg_off_dma)
32 #define MIO_EMM_DMA_INT_W1S(x) (0x38 + x->reg_off_dma)
33 #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma)
34 #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma)
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/Linux-v5.15/tools/perf/Documentation/
Dperf-stat.txt1 perf-stat(1)
5 ----
6 perf-stat - Run a command and gather performance counter statistics
9 --------
11 'perf stat' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf stat' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
13 'perf stat' [-e <EVENT> | --event=EVENT] [-a] record [-o file] \-- <command> [<options>]
14 'perf stat' report [-i file]
17 -----------
23 -------
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/Linux-v5.15/drivers/staging/sm750fb/
Dsm750.h1 /* SPDX-License-Identifier: GPL-2.0 */
83 /* common members */
95 /* all smi graphic adaptor got below attributes */
142 /* below attributes belong to info->fix, their value depends on specific adaptor*/
169 * output->channel ==> &crtc->channel
/Linux-v5.15/tools/power/x86/turbostat/
Dturbostat.83 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
41 MSRs are read as 64-bits, u32 truncates the displayed value to 32-bits.
51 Any string that does not match a key-word above is used
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/Linux-v5.15/drivers/ata/
Dpata_pcmcia.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pata_pcmcia.c - PCMCIA PATA controller driver.
4 * Copyright 2005-2006 Red Hat Inc, all rights reserved.
8 * Heavily based upon ide-cs.c
33 * pcmcia_set_mode - PCMCIA specific mode setup
40 * decode, which alas is embarrassingly common in the PC world
45 struct ata_device *master = &link->device[0]; in pcmcia_set_mode()
46 struct ata_device *slave = &link->device[1]; in pcmcia_set_mode()
51 if (memcmp(master->id + ATA_ID_FW_REV, slave->id + ATA_ID_FW_REV, in pcmcia_set_mode()
54 the same vendor - check serial */ in pcmcia_set_mode()
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/Linux-v5.15/include/uapi/linux/
Dkfd_ioctl.h30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
32 * - 1.4 - Indicate new SRAM EDC bit in device properties
33 * - 1.5 - Add SVM API
34 * - 1.6 - Query clear flags in SVM get_attr API
153 /* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
163 /* to KFD - indicates amount of memory present in
165 * from KFD - Number of entries filled by KFD.
230 __u32 event_trigger_data; /* from KFD - signal events only */
233 __u32 node_id; /* to KFD - only valid for certain
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/Linux-v5.15/drivers/net/ethernet/chelsio/cxgb3/
Dvsc8211.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
32 #include "common.h"
53 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
134 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status()
144 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status()
210 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status_fiber()
220 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status_fiber()
276 * Enable/disable auto MDI/MDI-X in forced link speed mode.
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/Linux-v5.15/include/acpi/
Dactbl.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl.h - Basic ACPI Table Definitions
6 * Copyright (C) 2000 - 2021, Intel Corp.
18 * by ACPICA. All other tables are consumed by the OS-dependent ACPI-related
21 * The RSDP and FACS do not use the common ACPI table header. All other ACPI
44 * All tables and structures must be byte-packed to match the ACPI
54 * essentially useless for dealing with packed data in on-disk formats or
63 * Master ACPI Table Header. This common header is used by all ACPI tables
82 * GAS - Generic Address Structure (ACPI 2.0+)
86 * 64-bit Address field must be performed with care.
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/Linux-v5.15/drivers/iommu/
Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
30 #include <soc/mediatek/smi.h>
123 ((((pdata)->flags) & (_x)) == (_x))
149 * |---A---|---B---|---C---|---D---|---E---|
150 * +--I/O--+------------Memory-------------+
156 * |---E---|---B---|---C---|---D---|
157 * +------------Memory-------------+
214 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_all()
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