Searched +full:sifive +full:- +full:blocks (Results 1 – 10 of 10) sorted by relevance
/Linux-v5.10/Documentation/devicetree/bindings/sifive/ |
D | sifive-blocks-ip-versioning.txt | 1 DT compatible string versioning for SiFive open-source IP blocks 4 strings for open-source SiFive IP blocks. HDL for these IP blocks 7 https://github.com/sifive/sifive-blocks 9 IP block-specific DT compatible strings are contained within the HDL, 10 in the form "sifive,<ip-block-name><integer version number>". 12 An example is "sifive,uart0" from: 14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43 16 Until these IP blocks (or IP integration) support version 17 auto-discovery, the maintainers of these IP blocks intend to increment 19 interface to these IP blocks changes, or when the functionality of the [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/pwm/ |
D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2020 SiFive, Inc. 4 --- 5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive PWM controller 11 - Yash Shah <yash.shah@sifive.com> 12 - Sagar Kadam <sagar.kadam@sifive.com> 13 - Paul Walmsley <paul.walmsley@sifive.com> 16 Unlike most other PWM controllers, the SiFive PWM controller currently [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/spi/ |
D | spi-sifive.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SiFive SPI controller 10 - Pragnesh Patel <pragnesh.patel@sifive.com> 11 - Paul Walmsley <paul.walmsley@sifive.com> 12 - Palmer Dabbelt <palmer@sifive.com> 15 - $ref: "spi-controller.yaml#" 20 - const: sifive,fu540-c000-spi [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/serial/ |
D | sifive-serial.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SiFive asynchronous serial interface (UART) 10 - Pragnesh Patel <pragnesh.patel@sifive.com> 11 - Paul Walmsley <paul.walmsley@sifive.com> 12 - Palmer Dabbelt <palmer@sifive.com> 15 - $ref: /schemas/serial.yaml# 20 - const: sifive,fu540-c000-uart [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/timer/ |
D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SiFive Core Local Interruptor 10 - Palmer Dabbelt <palmer@dabbelt.com> 11 - Anup Patel <anup.patel@wdc.com> 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16 interrupts. It directly connects to the timer and inter-processor interrupt [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/i2c/ |
D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores 4 - compatible : "opencores,i2c-ocores" 6 "sifive,fu540-c000-i2c", "sifive,i2c0" 8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt 10 - reg : bus address start and address range size of device 11 - clocks : handle to the controller clock; see the note below. 12 Mutually exclusive with opencores,ip-clock-frequency 13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz; 15 - #address-cells : should be <1> 16 - #size-cells : should be <0> [all …]
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/Linux-v5.10/drivers/tty/serial/ |
D | sifive.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * SiFive UART driver 5 * Copyright (C) 2018-2019 SiFive 18 * - drivers/tty/serial/pxa.c 19 * - drivers/tty/serial/amba-pl011.c 20 * - drivers/tty/serial/uartlite.c 21 * - drivers/tty/serial/omap-serial.c 22 * - drivers/pwm/pwm-sifive.c 25 * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of 26 * SiFive FE310-G000 v2p3 [all …]
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/Linux-v5.10/drivers/edac/ |
D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 40 levels are 0-4 (from low to high) and by default it is set to 2. 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 49 occurring on your machine in human-readable form. 59 Not all machines support hardware-driven error report. Some of those 60 provide a BIOS-driven error report mechanism via ACPI, using the 64 When this option is enabled, it will disable the hardware-driven 68 It should be noticed that keeping both GHES and a hardware-driven [all …]
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/Linux-v5.10/drivers/spi/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 13 dynamic device discovery; some are even write-only or read-only. 17 chips, analog to digital (and d-to-a) converters, and more. 44 If your system has an master-capable SPI controller (which 56 by providing a high-level interface to send memory-like commands. 111 supports spi-mem interface. 181 this code to manage the per-word or per-transfer accesses to the 211 Flash over 1/2/4-bit wide bus. Enable this option if you have a 219 This enables dedicated general purpose SPI/Microwire1-compatible 220 master mode interface (SSI1) for CLPS711X-based CPUs. [all …]
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/Linux-v5.10/drivers/gpio/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 57 non-sleeping contexts. They can make bitbanged serial protocols 115 tristate "GPIO driver for 74xx-ICs with MMIO access" 119 Say yes here to support GPIO functionality for 74xx-compatible ICs 135 If driver is built as a module it will be called gpio-altera. 285 tristate "Generic memory-mapped GPIO controller support (MMIO platform device)" 288 Say yes here to support basic platform_device memory-mapped GPIO controllers. 316 ICH-based chipsets. Currently supported devices: ICH6, ICH7, ICH8 334 depends on ARM # For <asm/mach-types.h> 352 bool "Loongson-2/3 GPIO support" [all …]
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