1 // SPDX-License-Identifier: GPL-2.0+
3  * SiFive UART driver
5  * Copyright (C) 2018-2019 SiFive
18  * - drivers/tty/serial/pxa.c
19  * - drivers/tty/serial/amba-pl011.c
20  * - drivers/tty/serial/uartlite.c
21  * - drivers/tty/serial/omap-serial.c
22  * - drivers/pwm/pwm-sifive.c
25  * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of
26  *   SiFive FE310-G000 v2p3
27  * - The tree/master/src/main/scala/devices/uart directory of
28  *   https://github.com/sifive/sifive-blocks/
30  * The SiFive UART design is not 8250-compatible.  The following common
32  * - Word lengths other than 8 bits
33  * - Break handling
34  * - Parity
35  * - Flow control
36  * - Modem signals (DSR, RI, etc.)
127 #define SIFIVE_SERIAL_NAME			"sifive-serial"
129 /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */
147  * sifive_serial_port - driver-specific data extension to struct uart_port
155  * Configuration data specific to this SiFive UART.
168  * Structure container-of macros
189  * __ssp_early_writel() - write to a SiFive serial port register (early)
202 	writel_relaxed(v, port->membase + offs);  in __ssp_early_writel()
206  * __ssp_early_readl() - read from a SiFive serial port register (early)
222 	return readl_relaxed(port->membase + offs);  in __ssp_early_readl()
226  * __ssp_writel() - write to a SiFive serial port register
238 	__ssp_early_writel(v, offs, &ssp->port);  in __ssp_writel()
242  * __ssp_readl() - read from a SiFive serial port register
255 	return __ssp_early_readl(&ssp->port, offs);  in __ssp_readl()
259  * sifive_serial_is_txfifo_full() - is the TXFIFO full?
262  * Read the transmit FIFO "full" bit, returning a non-zero value if the
266  * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO
276  * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO
292  * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO
296  * transmit buffer to the SiFive UART TX FIFO.
298  * Context: Any context.  Expects @ssp->port.lock to be held by caller.
302 	struct circ_buf *xmit = &ssp->port.state->xmit;  in __ssp_transmit_chars()
305 	if (ssp->port.x_char) {  in __ssp_transmit_chars()
306 		__ssp_transmit_char(ssp, ssp->port.x_char);  in __ssp_transmit_chars()
307 		ssp->port.icount.tx++;  in __ssp_transmit_chars()
308 		ssp->port.x_char = 0;  in __ssp_transmit_chars()
311 	if (uart_circ_empty(xmit) || uart_tx_stopped(&ssp->port)) {  in __ssp_transmit_chars()
312 		sifive_serial_stop_tx(&ssp->port);  in __ssp_transmit_chars()
317 		__ssp_transmit_char(ssp, xmit->buf[xmit->tail]);  in __ssp_transmit_chars()
318 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);  in __ssp_transmit_chars()
319 		ssp->port.icount.tx++;  in __ssp_transmit_chars()
322 	} while (--count > 0);  in __ssp_transmit_chars()
325 		uart_write_wakeup(&ssp->port);  in __ssp_transmit_chars()
328 		sifive_serial_stop_tx(&ssp->port);  in __ssp_transmit_chars()
332  * __ssp_enable_txwm() - enable transmit watermark interrupts
336  * on the SiFive UART referred to by @ssp.
340 	if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)  in __ssp_enable_txwm()
343 	ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_enable_txwm()
344 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_txwm()
348  * __ssp_enable_rxwm() - enable receive watermark interrupts
352  * on the SiFive UART referred to by @ssp.
356 	if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)  in __ssp_enable_rxwm()
359 	ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_enable_rxwm()
360 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_enable_rxwm()
364  * __ssp_disable_txwm() - disable transmit watermark interrupts
372 	if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK))  in __ssp_disable_txwm()
375 	ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK;  in __ssp_disable_txwm()
376 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_txwm()
380  * __ssp_disable_rxwm() - disable receive watermark interrupts
388 	if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK))  in __ssp_disable_rxwm()
391 	ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK;  in __ssp_disable_rxwm()
392 	__ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp);  in __ssp_disable_rxwm()
396  * __ssp_receive_char() - receive a byte from the UART
400  * Try to read a byte from the SiFive UART RX FIFO, referenced by
427  * __ssp_receive_chars() - receive multiple bytes from the UART
430  * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred
433  * Context: Expects ssp->port.lock to be held by caller.
441 	for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) {  in __ssp_receive_chars()
446 		ssp->port.icount.rx++;  in __ssp_receive_chars()
447 		uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL);  in __ssp_receive_chars()
450 	spin_unlock(&ssp->port.lock);  in __ssp_receive_chars()
451 	tty_flip_buffer_push(&ssp->port.state->port);  in __ssp_receive_chars()
452 	spin_lock(&ssp->port.lock);  in __ssp_receive_chars()
456  * __ssp_update_div() - calculate the divisor setting by the line rate
467 	div = DIV_ROUND_UP(ssp->clkin_rate, ssp->baud_rate) - 1;  in __ssp_update_div()
473  * __ssp_update_baud_rate() - set the UART "baud rate"
478  * SiFive UART described by @ssp and program it into the UART.  There may
485 	if (ssp->baud_rate == rate)  in __ssp_update_baud_rate()
488 	ssp->baud_rate = rate;  in __ssp_update_baud_rate()
493  * __ssp_set_stop_bits() - set the number of stop bits
497  * Program the SiFive UART referred to by @ssp to use @nstop stop bits.
510 	v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT;  in __ssp_set_stop_bits()
515  * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO
558 	spin_lock(&ssp->port.lock);  in sifive_serial_irq()
562 		spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
571 	spin_unlock(&ssp->port.lock);  in sifive_serial_irq()
614  * sifive_serial_clk_notifier() - clock post-rate-change notifier
620  * after a synchronous divide-by-two divider, so any CPU clock rate change
636 		 * left in the TX queue -- in other words, when the TX FIFO is  in sifive_serial_clk_notifier()
649 		udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate));  in sifive_serial_clk_notifier()
652 	if (event == POST_RATE_CHANGE && ssp->clkin_rate != cnd->new_rate) {  in sifive_serial_clk_notifier()
653 		ssp->clkin_rate = cnd->new_rate;  in sifive_serial_clk_notifier()
670 	if ((termios->c_cflag & CSIZE) != CS8)  in sifive_serial_set_termios()
671 		dev_err_once(ssp->port.dev, "only 8-bit words supported\n");  in sifive_serial_set_termios()
672 	if (termios->c_iflag & (INPCK | PARMRK))  in sifive_serial_set_termios()
673 		dev_err_once(ssp->port.dev, "parity checking not supported\n");  in sifive_serial_set_termios()
674 	if (termios->c_iflag & BRKINT)  in sifive_serial_set_termios()
675 		dev_err_once(ssp->port.dev, "BREAK detection not supported\n");  in sifive_serial_set_termios()
678 	nstop = (termios->c_cflag & CSTOPB) ? 2 : 1;  in sifive_serial_set_termios()
682 	rate = uart_get_baud_rate(port, termios, old, 0, ssp->clkin_rate / 16);  in sifive_serial_set_termios()
685 	spin_lock_irqsave(&ssp->port.lock, flags);  in sifive_serial_set_termios()
687 	/* Update the per-port timeout */  in sifive_serial_set_termios()
688 	uart_update_timeout(port, termios->c_cflag, rate);  in sifive_serial_set_termios()
690 	ssp->port.read_status_mask = 0;  in sifive_serial_set_termios()
695 	if ((termios->c_cflag & CREAD) == 0)  in sifive_serial_set_termios()
702 	spin_unlock_irqrestore(&ssp->port.lock, flags);  in sifive_serial_set_termios()
718 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_config_port()
724 	return -EINVAL;  in sifive_serial_verify_port()
729 	return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL;  in sifive_serial_type()
772 	struct earlycon_device *dev = con->data;  in early_sifive_serial_write()
773 	struct uart_port *port = &dev->port;  in early_sifive_serial_write()
781 	struct uart_port *port = &dev->port;  in early_sifive_serial_setup()
783 	if (!port->membase)  in early_sifive_serial_setup()
784 		return -ENODEV;  in early_sifive_serial_setup()
786 	dev->con->write = early_sifive_serial_write;  in early_sifive_serial_setup()
791 OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup);
792 OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0",
815 	struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_write()
824 	if (ssp->port.sysrq)  in sifive_serial_console_write()
827 		locked = spin_trylock(&ssp->port.lock);  in sifive_serial_console_write()
829 		spin_lock(&ssp->port.lock);  in sifive_serial_console_write()
834 	uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar);  in sifive_serial_console_write()
839 		spin_unlock(&ssp->port.lock);  in sifive_serial_console_write()
851 	if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS)  in sifive_serial_console_setup()
852 		return -ENODEV;  in sifive_serial_console_setup()
854 	ssp = sifive_serial_console_ports[co->index];  in sifive_serial_console_setup()
856 		return -ENODEV;  in sifive_serial_console_setup()
861 	return uart_set_options(&ssp->port, co, baud, parity, bits, flow);  in sifive_serial_console_setup()
872 	.index		= -1,
886 	sifive_serial_console_ports[ssp->port.line] = ssp;  in __ssp_add_console_port()
891 	sifive_serial_console_ports[ssp->port.line] = 0;  in __ssp_remove_console_port()
947 		return -EPROBE_DEFER;  in sifive_serial_probe()
950 	base = devm_ioremap_resource(&pdev->dev, mem);  in sifive_serial_probe()
952 		dev_err(&pdev->dev, "could not acquire device memory\n");  in sifive_serial_probe()
956 	clk = devm_clk_get(&pdev->dev, NULL);  in sifive_serial_probe()
958 		dev_err(&pdev->dev, "unable to find controller clock\n");  in sifive_serial_probe()
962 	id = of_alias_get_id(pdev->dev.of_node, "serial");  in sifive_serial_probe()
964 		dev_err(&pdev->dev, "missing aliases entry\n");  in sifive_serial_probe()
970 		dev_err(&pdev->dev, "too many UARTs (%d)\n", id);  in sifive_serial_probe()
971 		return -EINVAL;  in sifive_serial_probe()
975 	ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL);  in sifive_serial_probe()
977 		return -ENOMEM;  in sifive_serial_probe()
979 	ssp->port.dev = &pdev->dev;  in sifive_serial_probe()
980 	ssp->port.type = PORT_SIFIVE_V0;  in sifive_serial_probe()
981 	ssp->port.iotype = UPIO_MEM;  in sifive_serial_probe()
982 	ssp->port.irq = irq;  in sifive_serial_probe()
983 	ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH;  in sifive_serial_probe()
984 	ssp->port.ops = &sifive_serial_uops;  in sifive_serial_probe()
985 	ssp->port.line = id;  in sifive_serial_probe()
986 	ssp->port.mapbase = mem->start;  in sifive_serial_probe()
987 	ssp->port.membase = base;  in sifive_serial_probe()
988 	ssp->dev = &pdev->dev;  in sifive_serial_probe()
989 	ssp->clk = clk;  in sifive_serial_probe()
990 	ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier;  in sifive_serial_probe()
992 	r = clk_notifier_register(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
994 		dev_err(&pdev->dev, "could not register clock notifier: %d\n",  in sifive_serial_probe()
1000 	ssp->clkin_rate = clk_get_rate(ssp->clk);  in sifive_serial_probe()
1001 	ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;  in sifive_serial_probe()
1016 	r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags,  in sifive_serial_probe()
1017 			dev_name(&pdev->dev), ssp);  in sifive_serial_probe()
1019 		dev_err(&pdev->dev, "could not attach interrupt: %d\n", r);  in sifive_serial_probe()
1025 	r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_probe()
1027 		dev_err(&pdev->dev, "could not add uart: %d\n", r);  in sifive_serial_probe()
1035 	free_irq(ssp->port.irq, ssp);  in sifive_serial_probe()
1037 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_probe()
1047 	uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port);  in sifive_serial_remove()
1048 	free_irq(ssp->port.irq, ssp);  in sifive_serial_remove()
1049 	clk_notifier_unregister(ssp->clk, &ssp->clk_notifier);  in sifive_serial_remove()
1055 	{ .compatible = "sifive,fu540-c000-uart0" },
1056 	{ .compatible = "sifive,uart0" },
1099 MODULE_DESCRIPTION("SiFive UART serial driver");