Searched +full:sifive +full:- +full:blocks +full:- +full:ip +full:- +full:versioning (Results 1 – 4 of 4) sorted by relevance
1 DT compatible string versioning for SiFive open-source IP blocks4 strings for open-source SiFive IP blocks. HDL for these IP blocks7 https://github.com/sifive/sifive-blocks9 IP block-specific DT compatible strings are contained within the HDL,10 in the form "sifive,<ip-block-name><integer version number>".12 An example is "sifive,uart0" from:14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L4316 Until these IP blocks (or IP integration) support version17 auto-discovery, the maintainers of these IP blocks intend to increment19 interface to these IP blocks changes, or when the functionality of the[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)2 # Copyright (C) 2020 SiFive, Inc.4 ---5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: SiFive PWM controller11 - Sagar Kadam <sagar.kadam@sifive.com>12 - Paul Walmsley <paul.walmsley@sifive.com>15 Unlike most other PWM controllers, the SiFive PWM controller currently19 achievable period. PWM RTL that corresponds to the IP block version[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: SiFive SPI controller10 - Pragnesh Patel <pragnesh.patel@sifive.com>11 - Paul Walmsley <paul.walmsley@sifive.com>12 - Palmer Dabbelt <palmer@sifive.com>15 - $ref: "spi-controller.yaml#"20 - enum:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: SiFive Core Local Interruptor10 - Palmer Dabbelt <palmer@dabbelt.com>11 - Anup Patel <anup.patel@wdc.com>14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor16 interrupts. It directly connects to the timer and inter-processor interrupt[all …]