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/Linux-v6.1/drivers/net/ethernet/qualcomm/emac/
Demac-sgmii.c5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
14 #include "emac-sgmii.h"
88 /* Initialize the SGMII link between the internal and external PHYs. */
121 net_err_ratelimited("%s: failed to clear SGMII irq: status:0x%x bits:0x%x\n", in emac_sgmii_irq_clear()
158 /* The SGMII is capable of recovering from some decode in emac_sgmii_interrupt()
193 * SGMII in emac_sgmii_reset_prepare()
214 struct emac_sgmii *sgmii = &adpt->phy; in emac_sgmii_common_open() local
217 if (sgmii->irq) { in emac_sgmii_common_open()
222 writel(0, sgmii->base + EMAC_SGMII_PHY_INTERRUPT_MASK); in emac_sgmii_common_open()
224 ret = request_irq(sgmii->irq, emac_sgmii_interrupt, 0, in emac_sgmii_common_open()
[all …]
DMakefile8 qcom-emac-objs := emac.o emac-mac.o emac-phy.o emac-sgmii.o emac-ethtool.o \
9 emac-sgmii-fsm9900.o emac-sgmii-qdf2432.o \
10 emac-sgmii-qdf2400.o
Demac-sgmii-qdf2400.c5 /* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
46 /* SGMII digital lane register values */
185 /* SGMII lane-x init */ in emac_sgmii_init_qdf2400()
202 netdev_err(adpt->netdev, "SGMII failed to start\n"); in emac_sgmii_init_qdf2400()
211 /* Mask out all the SGMII Interrupt */ in emac_sgmii_init_qdf2400()
Demac-sgmii-qdf2432.c5 /* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
44 /* SGMII digital lane register values */
172 /* SGMII lane-x init */ in emac_sgmii_init_qdf2432()
189 netdev_err(adpt->netdev, "SGMII failed to start\n"); in emac_sgmii_init_qdf2432()
198 /* Mask out all the SGMII Interrupt */ in emac_sgmii_init_qdf2432()
/Linux-v6.1/drivers/net/dsa/sja1105/
DKconfig17 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
18 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
19 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
20 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
23 - SJA1110C (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 7 ports)
24 - SJA1110D (Gen. 3, SGMII, TT-Ethernet, no 100base-TX PHY, 7 ports)
/Linux-v6.1/Documentation/devicetree/bindings/net/
Dsocfpga-dwmac.txt27 altr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter
29 This device node has additional phandle dependency, the sgmii converter:
32 - compatible : Should be altr,gmii-to-sgmii-2.0
38 compatible = "altr,gmii-to-sgmii-2.0";
55 phy-mode = "sgmii";
56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
Dqcom-emac.txt3 This network controller consists of two devices: a MAC and an SGMII
20 - compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
61 compatible = "qcom,fsm9900-emac-sgmii";
107 compatible = "qcom,qdf2432-emac-sgmii";
/Linux-v6.1/arch/mips/cavium-octeon/executive/
Dcvmx-helper-sgmii.c29 * Functions for SGMII initialization, configuration,
45 * Perform initialization required only once for an SGMII port.
67 * interval. SGMII specifies a 1.6ms interval. in __cvmx_helper_sgmii_hardware_init_one_time()
78 /* SGMII */ in __cvmx_helper_sgmii_hardware_init_one_time()
89 * In SGMII PHY mode, tx_Config_Reg<D15:D0> is in __cvmx_helper_sgmii_hardware_init_one_time()
90 * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, in __cvmx_helper_sgmii_hardware_init_one_time()
158 cvmx_dprintf("SGMII%d: Timeout waiting for port %d " in __cvmx_helper_sgmii_hardware_init_link()
167 * sgmii negotiation starts. in __cvmx_helper_sgmii_hardware_init_link()
177 * that sgmii autonegotiation is complete. In MAC mode this in __cvmx_helper_sgmii_hardware_init_link()
185 /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ in __cvmx_helper_sgmii_hardware_init_link()
[all …]
/Linux-v6.1/Documentation/networking/dsa/
Dsja1105.rst12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
19 - SJA1110C: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
20 - SJA1110D: Third generation, TTEthernet, SGMII, 100base-T1
54 SGMII no yes
420 4 xMII xMII SGMII
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/
Dqca8k.yaml86 qca,sgmii-rxclk-falling-edge:
90 the QCA8327 with CPU port 0 set to SGMII.
92 qca,sgmii-txclk-falling-edge:
97 qca,sgmii-enable-pll:
100 For SGMII CPU port, explicitly enable PLL, TX and RX chain along with
102 the SGMII port will not initialize. When used on the QCA8337, revision 3
104 SGMII on the QCA8337, it is advised to set this unless a communication
270 phy-mode = "sgmii";
272 qca,sgmii-rxclk-falling-edge;
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-ls1046a-qds.dts35 sgmii-s1-p1 = &sgmii_phy_s1_p1;
36 sgmii-s1-p2 = &sgmii_phy_s1_p2;
37 sgmii-s1-p3 = &sgmii_phy_s1_p3;
38 sgmii-s1-p4 = &sgmii_phy_s1_p4;
39 sgmii-s4-p1 = &sgmii_phy_s4_p1;
197 phy-connection-type = "sgmii";
202 phy-connection-type = "sgmii";
217 phy-connection-type = "sgmii";
222 phy-connection-type = "sgmii";
Dfsl-ls1028a-qds-9999.dts40 phy-mode = "sgmii";
47 phy-mode = "sgmii";
54 phy-mode = "sgmii";
61 phy-mode = "sgmii";
Dfsl-ls1043a-qds.dts27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
30 sgmii-riser-s4-p1 = &sgmii_phy_s4_p1;
179 phy-connection-type = "sgmii";
184 phy-connection-type = "sgmii";
199 phy-connection-type = "sgmii";
204 phy-connection-type = "sgmii";
Dfsl-ls1028a-qds-899b.dts38 phy-mode = "sgmii";
47 phy-mode = "sgmii";
54 phy-mode = "sgmii";
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dp5040ds.dts179 phy-connection-type = "sgmii";
183 phy-connection-type = "sgmii";
187 phy-connection-type = "sgmii";
191 phy-connection-type = "sgmii";
207 phy-connection-type = "sgmii";
211 phy-connection-type = "sgmii";
215 phy-connection-type = "sgmii";
219 phy-connection-type = "sgmii";
314 hydra_sg_slot2: sgmii-mdio@28 {
337 hydra_sg_slot3: sgmii-mdio@68 {
[all …]
Dt4240rdb.dts157 phy-connection-type = "sgmii";
162 phy-connection-type = "sgmii";
167 phy-connection-type = "sgmii";
172 phy-connection-type = "sgmii";
197 phy-connection-type = "sgmii";
202 phy-connection-type = "sgmii";
207 phy-connection-type = "sgmii";
212 phy-connection-type = "sgmii";
Dp4080ds.dts197 phy-connection-type = "sgmii";
202 phy-connection-type = "sgmii";
207 phy-connection-type = "sgmii";
212 phy-connection-type = "sgmii";
224 phy-connection-type = "sgmii";
229 phy-connection-type = "sgmii";
234 phy-connection-type = "sgmii";
239 phy-connection-type = "sgmii";
Dt4240qds.dts481 phy-connection-type = "sgmii";
486 phy-connection-type = "sgmii";
491 phy-connection-type = "sgmii";
496 phy-connection-type = "sgmii";
506 phy-connection-type = "sgmii";
557 phy-connection-type = "sgmii";
562 phy-connection-type = "sgmii";
567 phy-connection-type = "sgmii";
572 phy-connection-type = "sgmii";
582 phy-connection-type = "sgmii";
/Linux-v6.1/drivers/net/phy/
Dmxl-gpy.c63 /* SGMII */
392 /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is in gpy_config_aneg()
399 /* There is a design constraint in GPY2xx device where SGMII AN is in gpy_config_aneg()
402 * again, SGMII AN is not triggered and hence no new in-band message in gpy_config_aneg()
403 * from GPY to MAC side SGMII. in gpy_config_aneg()
405 * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII in gpy_config_aneg()
411 * retriggerring SGMII AN. in gpy_config_aneg()
413 * reboot), polling of TPI link status is not needed and SGMII AN is in gpy_config_aneg()
416 * retriggering SGMII AN. Note: in case of speed change, GPY FW will in gpy_config_aneg()
417 * initiate SGMII AN. in gpy_config_aneg()
[all …]
/Linux-v6.1/arch/mips/boot/dts/cavium-octeon/
Docteon_68xx.dts74 cavium,qlm-trim = "4,sgmii";
83 cavium,qlm-trim = "4,sgmii";
92 cavium,qlm-trim = "4,sgmii";
101 cavium,qlm-trim = "4,sgmii";
118 cavium,qlm-trim = "0,sgmii";
127 cavium,qlm-trim = "0,sgmii";
136 cavium,qlm-trim = "0,sgmii";
145 cavium,qlm-trim = "0,sgmii";
162 cavium,qlm-trim = "2,sgmii";
171 cavium,qlm-trim = "2,sgmii";
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dbcm958625-meraki-alamo.dtsi119 phy-mode = "sgmii";
120 qca,sgmii-enable-pll;
121 qca,sgmii-txclk-falling-edge;
197 phy-mode = "sgmii";
198 qca,sgmii-enable-pll;
199 qca,sgmii-txclk-falling-edge;
/Linux-v6.1/arch/mips/include/asm/octeon/
Dcvmx-helper-sgmii.h31 * Functions for SGMII initialization, configuration,
39 * Probe a SGMII interface and determine the number of ports
40 * connected to it. The SGMII interface should still be down after
51 * Bringup and enable a SGMII interface. After this call packet
/Linux-v6.1/arch/mips/boot/dts/mscc/
Docelot_pcb120.dts98 phy-mode = "sgmii";
105 phy-mode = "sgmii";
112 phy-mode = "sgmii";
119 phy-mode = "sgmii";
/Linux-v6.1/drivers/net/ethernet/freescale/fman/
Dfman_memac.c25 /* SGMII Control defines */
33 /* SGMII Device Ability for SGMII defines */
43 /* SGMII IF Mode defines */
496 /* SGMII mode */ in setup_sgmii_internal_phy()
519 /* Device ability according to SGMII specification */ in setup_sgmii_internal_phy()
523 /* Adjust link timer for SGMII - in setup_sgmii_internal_phy()
524 * According to Cisco SGMII specification the timer should be 1.6 ms. in setup_sgmii_internal_phy()
526 * - When running as 1G SGMII, Serdes clock is 125 MHz, so in setup_sgmii_internal_phy()
529 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so in setup_sgmii_internal_phy()
532 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII, in setup_sgmii_internal_phy()
[all …]
/Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/
Dstmmac_pcs.h16 /* PCS registers (AN/TBI/SGMII/RGMII) offsets */
30 #define GMAC_AN_CTRL_SGMRAL BIT(18) /* SGMII RAL Control */
48 * dwmac_pcs_isr - TBI, RTBI, or SGMII PHY ISR
99 * @srgmi_ral: to manage MAC-2-MAC SGMII connections.
103 * configure SGMII RAL.

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