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/Linux-v5.10/arch/arm/mach-bcm/
Dplatsmp.c33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
120 /* Ensure the write is visible to the secondary core */ in nsp_write_lut()
141 * The ROM code has the secondary cores looping, waiting for an event.
143 * secondary boot register. When a core finds those bits contain its
147 * address back to the secondary boot register, and finally jumps to
151 * - Encode the (hardware) CPU id with the bottom bits of the secondary
153 * - Write that value into the secondary boot register.
154 * - Generate an event to wake up the secondary CPU(s).
[all …]
/Linux-v5.10/Documentation/admin-guide/blockdev/drbd/
Dnode-states-8.dot2 Secondary -> Primary [ label = "ioctl_set_state()" ]
3 Primary -> Secondary [ label = "ioctl_set_state()" ]
7 Secondary -> Primary [ label = "recv state packet" ]
8 Primary -> Secondary [ label = "recv state packet" ]
10 Secondary -> Unknown [ label = "connection lost" ]
12 Unknown -> Secondary [ label = "connected" ]
/Linux-v5.10/arch/sparc/include/uapi/asm/
Dasi.h130 #define ASI_AIUS 0x11 /* Secondary, user */
132 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
134 #define ASI_S 0x81 /* Secondary, implicit */
136 #define ASI_SNF 0x83 /* Secondary, no fault */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
161 * secondary, user
231 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
242 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
[all …]
/Linux-v5.10/arch/arm64/include/asm/
Dsmp.h20 /* Fatal system error detected by secondary CPU, crash the system */
70 * Called from the secondary holding pen, this is the secondary CPU entry point.
75 * Initial data for bringing up a secondary CPU.
76 * @stack - sp for the secondary CPU
77 * @status - Result passed back from the secondary CPU to
124 * The calling secondary CPU has detected serious configuration mismatch,
135 * If a secondary CPU enters the kernel but fails to come online,
/Linux-v5.10/drivers/ide/
Dide-generic.c43 static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary) in ide_generic_check_pci_legacy_iobases() argument
53 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
59 *primary = *secondary = 1; in ide_generic_check_pci_legacy_iobases()
68 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
81 int i, rc = 0, primary = 0, secondary = 0; in ide_generic_init() local
83 ide_generic_check_pci_legacy_iobases(&primary, &secondary); in ide_generic_init()
92 if (secondary == 0) in ide_generic_init()
/Linux-v5.10/Documentation/sparc/oradax/
Ddax-hv-api.txt172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
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/Linux-v5.10/sound/soc/qcom/qdsp6/
Dq6afe-dai.c598 {"Secondary MI2S Playback", NULL, "SEC_MI2S_RX"},
611 {"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"},
612 {"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"},
613 {"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"},
614 {"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"},
615 {"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"},
616 {"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"},
617 {"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"},
618 {"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"},
656 {"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"},
[all …]
Dq6afe.h30 /* Clock ID for Secondary I2S IBIT */
32 /* Clock ID for Secondary I2S EBIT */
79 /* Clock ID for Secondary PCM IBIT */
81 /* Clock ID for Secondary PCM EBIT */
102 /** Clock ID for Secondary TDM IBIT */
104 /** Clock ID for Secondary TDM EBIT */
/Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
/Linux-v5.10/arch/arm/mach-mmp/
Dirqs.h180 /* secondary interrupt of INT #4 */
185 /* secondary interrupt of INT #5 */
190 /* secondary interrupt of INT #9 */
196 /* secondary interrupt of INT #17 */
204 /* secondary interrupt of INT #35 */
221 /* secondary interrupt of INT #51 */
226 /* secondary interrupt of INT #55 */
/Linux-v5.10/arch/arm/mach-mvebu/
Dheadsmp.S2 * SMP support: Entry point for secondary CPUs
14 * This file implements the assembly entry point for secondary CPUs in
27 * Armada XP specific entry point for secondary CPUs.
28 * We add the CPU to the coherency fabric and then jump to secondary
/Linux-v5.10/arch/arm/mach-omap2/
Domap-headsmp.S3 * Secondary CPU startup routine source file.
21 /* Physical address needed since MMU not enabled yet on secondary core */
36 * OMAP5 specific entry point for secondary CPU to jump from ROM
38 * secondary core is held until we're ready for it to initialise.
75 * OMAP4 specific entry point for secondary CPU to jump from ROM
77 * secondary core is held until we're ready for it to initialise.
/Linux-v5.10/arch/arm/plat-versatile/
Dplatsmp.c47 * calibrations on the secondary CPU while the requesting CPU is using
74 * and the secondary one in versatile_boot_secondary()
79 * This is really belt and braces; we hold unintended secondary in versatile_boot_secondary()
87 * Send the secondary CPU a soft interrupt, thereby causing in versatile_boot_secondary()
103 * now the secondary core is starting up let it run its in versatile_boot_secondary()
/Linux-v5.10/arch/arm/mach-spear/
Dplatsmp.c62 * and the secondary one in spear13xx_boot_secondary()
67 * The secondary processor is waiting to be released from in spear13xx_boot_secondary()
86 * now the secondary core is starting up let it run its in spear13xx_boot_secondary()
118 * Write the address of secondary startup into the system-wide location in spear13xx_smp_prepare_cpus()
120 * soft interrupt, and then the secondary CPU branches to this address. in spear13xx_smp_prepare_cpus()
/Linux-v5.10/arch/arm/mach-prima2/
Dplatsmp.c64 * write the address of secondary startup into the clkc register in sirfsoc_boot_secondary()
67 * waiting for. This would wake up the secondary core from WFE in sirfsoc_boot_secondary()
83 * The secondary processor is waiting to be released from in sirfsoc_boot_secondary()
94 * Send the secondary CPU SEV, thereby causing the boot monitor to read in sirfsoc_boot_secondary()
109 * now the secondary core is starting up let it run its in sirfsoc_boot_secondary()
/Linux-v5.10/Documentation/arm/samsung/
Dbootloader-interface.rst28 0x1c exynos4_secondary_startup Secondary CPU boot
29 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
44 0x00 exynos4_secondary_startup Secondary CPU boot
45 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
46 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
60 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
72 0x0908 Non-zero Secondary CPU boot up indicator
/Linux-v5.10/arch/sparc/kernel/
Dsbus.c263 #define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
264 #define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
265 #define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
287 /* Clear primary/secondary error status bits. */ in sysio_ue_handler()
310 printk("SYSIO[%x]: Secondary UE errors [", portid); in sysio_ue_handler()
336 #define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
337 #define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
338 #define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
361 /* Clear primary/secondary error status bits. */ in sysio_ce_handler()
389 printk("SYSIO[%x]: Secondary CE errors [", portid); in sysio_ce_handler()
[all …]
Dpci_sabre.c35 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
36 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
37 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
46 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
47 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
123 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
124 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
125 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
126 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
209 /* Clear the primary/secondary error status bits. */ in sabre_ue_intr()
[all …]
/Linux-v5.10/drivers/net/wireless/intel/iwlwifi/mvm/
Dcoex.c271 struct ieee80211_chanctx_conf *secondary; member
312 swap(data->primary, data->secondary); in iwl_mvm_bt_coex_tcm_based_ci()
388 data->secondary = data->primary; in iwl_mvm_bt_notif_iterator()
404 data->secondary = data->primary; in iwl_mvm_bt_notif_iterator()
407 /* there is low latency vif - we will be secondary */ in iwl_mvm_bt_notif_iterator()
408 data->secondary = chanctx_conf; in iwl_mvm_bt_notif_iterator()
413 else if (data->secondary == chanctx_conf) in iwl_mvm_bt_notif_iterator()
424 else if (!data->secondary) in iwl_mvm_bt_notif_iterator()
425 /* if secondary is not NULL, it might be a GO */ in iwl_mvm_bt_notif_iterator()
426 data->secondary = chanctx_conf; in iwl_mvm_bt_notif_iterator()
[all …]
/Linux-v5.10/arch/powerpc/platforms/powernv/
Dsubcore.h8 #define SYNC_STEP_UNSPLIT 1 /* Set by secondary when it sees unsplit */
9 #define SYNC_STEP_REAL_MODE 2 /* Set by secondary when in real mode */
10 #define SYNC_STEP_FINISHED 3 /* Set by secondary when split/unsplit is done */
/Linux-v5.10/arch/arm/mach-pxa/include/mach/
Dregs-ac97.h30 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
32 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
60 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
62 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
98 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
100 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
/Linux-v5.10/arch/alpha/kernel/
Dsys_sable.c273 *48 PCI 0 slot 0 A secondary bus
274 *49 PCI 0 slot 0 B secondary bus
275 *50 PCI 0 slot 0 C secondary bus
276 *51 PCI 0 slot 0 D secondary bus
277 *52 PCI 0 slot 1 A secondary bus
278 *53 PCI 0 slot 1 B secondary bus
279 *54 PCI 0 slot 1 C secondary bus
280 *55 PCI 0 slot 1 D secondary bus
281 *56 PCI 0 slot 2 A secondary bus
282 *57 PCI 0 slot 2 B secondary bus
[all …]
/Linux-v5.10/include/linux/
Dmmu_notifier.h64 * should tear down all secondary mmu mappings and freeze the
65 * secondary mmu. If this method isn't implemented you've to
67 * through the secondary mmu by the time the last thread with
74 * through the secondary mmu are terminated by the time the
89 * accesses to the page through the secondary MMUs and not
91 * Start-end is necessary in case the secondary MMU is mapping the page
102 * in the secondary pte, but it may omit flushing the secondary tlb.
111 * the secondary pte. This is used to know if the page is
113 * down the secondary mapping on the page.
166 * any secondary tlb before doing the final free on the
[all …]
/Linux-v5.10/certs/
Dsystem_keyring.c48 * addition by both builtin and secondary keyrings
51 * being vouched for by a key in either the built-in or the secondary system
60 /* If we have a secondary trusted keyring, then that contains a link in restrict_link_by_builtin_and_secondary_trusted()
66 /* Allow the builtin keyring to be added to the secondary */ in restrict_link_by_builtin_and_secondary_trusted()
74 * Allocate a struct key_restriction for the "builtin and secondary trust"
84 panic("Can't allocate secondary trusted keyring restriction\n"); in get_builtin_and_secondary_restriction()
120 panic("Can't allocate secondary trusted keyring\n"); in system_trusted_keyring_init()
/Linux-v5.10/drivers/iio/imu/inv_mpu6050/
Dinv_mpu_acpi.c154 unsigned short primary, secondary; in inv_mpu_acpi_create_mux_client() local
157 &secondary); in inv_mpu_acpi_create_mux_client()
158 if (!ret && secondary) { in inv_mpu_acpi_create_mux_client()
161 info.addr = secondary; in inv_mpu_acpi_create_mux_client()
170 return 0; /* no secondary addr, which is OK */ in inv_mpu_acpi_create_mux_client()

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