| /Linux-v5.10/Documentation/devicetree/bindings/mmc/ |
| D | brcm,sdhci-iproc.txt | 1 Broadcom IPROC SDHCI controller
4 by mmc.txt and the properties that represent the IPROC SDHCI controller.
7 - compatible : Should be one of the following
8 "brcm,bcm2835-sdhci"
9 "brcm,bcm2711-emmc2"
10 "brcm,sdhci-iproc-cygnus"
11 "brcm,sdhci-iproc"
13 Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
14 bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
16 Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
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| D | marvell,xenon-sdhci.txt | 1 Marvell Xenon SDHCI Controller device tree bindings
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
22 - clock-names:
27 - reg:
28 * For "marvell,armada-3700-sdhci", two register areas.
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| D | nvidia,tegra20-sdhci.txt | 7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
18 - clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
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| D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
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| D | sdhci-msm.txt | 1 * Qualcomm SDHCI controller (sdhci-msm)
4 and the properties used by the sdhci-msm driver.
7 - compatible: Should contain a SoC-specific string and a IP version string:
9 "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
10 "qcom,sdhci-msm-v5" for sdcc version 5.0
13 string is added to support this change - "qcom,sdhci-msm-v5".
15 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
16 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
17 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
18 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
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| D | aspeed,sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
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| D | sdhci-pxa.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA SDHCI v2/v3 bindings
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: marvell,armada-380-sdhci
23 reg-names:
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| D | arasan,sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Device Tree Bindings for the Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
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| D | sdhci-of-dwcmshc.txt | 4 - compatible: should be one of the following:
5 "snps,dwcmshc-sdhci"
6 - reg: offset and length of the register set for the device.
7 - interrupts: a single interrupt specifier.
8 - clocks: Array of clocks required for SDHCI; requires at least one for
10 - clock-names: Array of names corresponding to clocks property; shall be
14 sdhci2: sdhci@aa0000 {
15 compatible = "snps,dwcmshc-sdhci";
19 bus-width = <8>;
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| D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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| D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - ti,am654-sdhci-5.1
20 - ti,j721e-sdhci-8bit
21 - ti,j721e-sdhci-4bit
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| D | microchip,dw-sparx5-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml"
13 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
31 clock-names:
33 - const: core
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| /Linux-v5.10/Documentation/devicetree/bindings/clock/ |
| D | mvebu-gated-clock.txt | 12 -----------------------------------
21 17 sdio SDHCI Host
29 -----------------------------------
35 8 audio Audio Cntrl
40 17 sdio SDHCI Host
56 -----------------------------------
64 8 pex0 PCIe 0
83 -----------------------------------
87 8 pex0 PCIe 0
97 -----------------------------------
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| /Linux-v5.10/drivers/mmc/host/ |
| D | sdhci-s3c.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/mmc/host/sdhci-s3c.c
9 * SDHCI (HSMMC) support for Samsung SoC
14 #include <linux/dma-mapping.h>
16 #include <linux/platform_data/mmc-sdhci-s3c.h>
29 #include "sdhci.h"
63 #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD BIT(8)
86 #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8)
87 #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8)
88 #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8)
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| D | sdhci-st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for SDHCI on STMicroelectronics SoCs
9 * Based on sdhci-cns3xxx.c
18 #include "sdhci-pltfm.h"
31 #define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT BIT(8)
59 #define ST_MMC_CCONFIG_3P3_VOLT BIT(8)
72 #define ST_MMC_CCONFIG_DDR50 BIT(8)
78 #define ST_MMC_CCONFIG_TUNING_FOR_SDR50 BIT(8)
88 #define ST_TOP_MMC_DLY_FIX_OFF(x) (x - 0x8)
97 #define ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE BIT(8)
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| D | sdhci-pltfm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-pltfm.c Support for SDHCI platform devices
14 * SDHCI platform devices
16 * Inspired by sdhci-pci.c, by Pierre Ossman
26 #include "sdhci-pltfm.h"
32 return clk_get_rate(pltfm_host->clk); in sdhci_pltfm_clk_get_max_clock()
45 if (device_property_present(dev, "sdhci,wp-inverted") || in sdhci_wp_inverted()
46 device_property_present(dev, "wp-inverted")) in sdhci_wp_inverted()
49 /* Old device trees don't have the wp-inverted property. */ in sdhci_wp_inverted()
61 struct device_node *np = pdev->dev.of_node; in sdhci_get_compatibility()
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| D | sdhci-of-aspeed.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
37 struct aspeed_sdhci *sdhci, in aspeed_sdc_configure_8bit_mode() argument
42 /* Set/clear 8 bit mode */ in aspeed_sdc_configure_8bit_mode()
43 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
44 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
46 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
48 info &= ~sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
49 writel(info, sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
50 spin_unlock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
76 need to overwrite SDHCI IO memory accessors.
84 and performing I/O to a SDHCI controller through a bus that
85 implements a hardware byte swapper using a 32-bit datum.
90 This is the case for the Nintendo Wii SDHCI.
93 tristate "SDHCI support on PCI bus"
112 proprietary controller is unnecessary because the SDHCI driver
114 disabled, it will steal the MMC cards away - rendering them
121 tristate "SDHCI support for ACPI enumerated SDHCI controllers"
125 This selects support for ACPI enumerated SDHCI controllers,
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| D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-pltfm.h"
55 * On some SoCs the syscon area has a feature where the upper 16-bits of
56 * each 32-bit register act as a write mask for the lower 16-bits. This allows
64 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
68 * @shift: Bit offset within @reg of this field (or -1 if not avail)
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| D | sdhci-pxav2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 #include "sdhci.h"
25 #include "sdhci-pltfm.h"
35 #define SDCLK_SEL_SHIFT 8
46 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); in pxav2_reset()
47 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in pxav2_reset()
58 if (pdata && pdata->clk_delay_sel == 1) { in pxav2_reset()
59 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
62 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav2_reset()
67 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
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| D | sdhci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-pltfm.h"
45 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8
110 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
176 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
178 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
184 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
197 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
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| /Linux-v5.10/arch/arm/mach-s3c/ |
| D | setup-sdhci-gpio-s3c24xx.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
8 // Based on mach-s3c64xx/setup-sdhci-gpio.c
17 #include "regs-gpio.h"
18 #include "gpio-samsung.h"
19 #include "gpio-cfg.h"
20 #include "sdhci.h"
30 s3c_gpio_cfgrange_nopull(S3C2410_GPL(8), 2, S3C_GPIO_SFN(2)); in s3c2416_setup_sdhci1_cfg_gpio()
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| /Linux-v5.10/arch/arm/boot/dts/ |
| D | s3c64xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,arm1176jzf-s";
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
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| D | qcom-apq8084-ifc6540.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8084.dtsi"
3 #include "qcom-pma8084.dtsi"
7 compatible = "qcom,apq8084-sbc", "qcom,apq8084";
15 stdout-path = "serial0:115200n8";
23 sdhci@f9824900 {
24 bus-width = <8>;
25 non-removable;
29 sdhci@f98a4900 {
30 cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>;
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| /Linux-v5.10/drivers/clk/samsung/ |
| D | clk-s3c64xx.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 #include "clk-pll.h"
98 /* S3C6400-specific parent clocks. */
103 /* S3C6410-specific parent clocks. */
163 DIV(HCLK, "hclk", "hclkx2", CLK_DIV0, 8, 1),
171 DIV(DOUT_MMC2, "dout_mmc2", "mout_mmc2", CLK_DIV1, 8, 4),
177 DIV(DOUT_AUDIO0, "dout_audio0", "mout_audio0", CLK_DIV2, 8, 4),
214 GATE_BUS(HCLK_2D, "hclk_2d", "hclk", HCLK_GATE, 8),
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