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/Linux-v6.1/Documentation/devicetree/bindings/net/can/
Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
[all …]
/Linux-v6.1/drivers/staging/axis-fifo/
Daxis-fifo.txt1 Xilinx AXI-Stream FIFO v4.1 IP core
3 This IP core has read and write AXI-Stream FIFOs, the contents of which can
4 be accessed from the AXI4 memory-mapped interface. This is useful for
11 Currently supports only store-forward mode with a 32-bit
12 AXI4-Lite interface. DOES NOT support:
13 - cut-through mode
14 - AXI4 (non-lite)
17 - compatible: Should be "xlnx,axi-fifo-mm-s-4.1"
18 - interrupt-names: Should be "interrupt"
19 - interrupt-parent: Should be <&intc>
[all …]
Daxis-fifo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core
12 /* ----------------------------
14 * ----------------------------
39 /* ----------------------------
41 * ----------------------------
49 /* ----------------------------
51 * ----------------------------
70 /* ----------------------------
72 * ----------------------------
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/net/
Daltr,tse.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-controller.yaml#"
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - $ref: "ethernet-phy.yaml#"
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
[all …]
Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
[all …]
Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: "snps,dwmac.yaml#"
27 - items:
28 - enum:
[all …]
/Linux-v6.1/Documentation/networking/device_drivers/can/freescale/
Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
23 while the mailbox mode uses a software FIFO with a depth of up to 62
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
[all …]
/Linux-v6.1/include/linux/
Dqcom-geni-se.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
15 * @GENI_SE_FIFO: FIFO mode. Data is transferred with SE FIFO
55 * struct geni_se - GENI Serial Engine
210 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
287 * geni_se_read_proto() - Read the protocol configured for a serial engine
296 val = readl_relaxed(se->base + GENI_FW_REVISION_RO); in geni_se_read_proto()
302 * geni_se_setup_m_cmd() - Setup the primary sequencer
315 writel(m_cmd, se->base + SE_GENI_M_CMD0); in geni_se_setup_m_cmd()
319 * geni_se_setup_s_cmd() - Setup the secondary sequencer
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mmc/
Dsynopsys-dw-mshc-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "mmc-controller.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
20 reset-names:
23 clock-frequency:
29 fifo-depth:
31 The maximum size of the tx/rx fifo's. If this property is not
[all …]
Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "synopsys-dw-mshc-common.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
19 - altr,socfpga-dw-mshc
20 - img,pistachio-dw-mshc
21 - snps,dw-mshc
36 clock-names:
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/sound/
Dfsl,esai.txt3 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
10 - compatible : Compatible list, should contain one of the following
12 "fsl,imx35-esai",
13 "fsl,vf610-esai",
14 "fsl,imx6ull-esai",
15 "fsl,imx8qm-esai",
17 - reg : Offset and length of the register set for the device.
19 - interrupts : Contains the spdif interrupt.
21 - dmas : Generic dma devicetree binding as described in
24 - dma-names : Two dmas have to be defined, "tx" and "rx".
[all …]
/Linux-v6.1/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/Linux-v6.1/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/Linux-v6.1/drivers/net/ethernet/sgi/
Dmeth.h4 #define TX_RING_ENTRIES 64 /* 64-512?*/
11 #define METH_RX_HEAD 34 /* status + 3 quad garbage-fill + 2 byte zero-pad */
32 * It consists of header, 0-3 concatination
43 u64 data_len:16; /*Length of valid data in bytes-1*/
48 u64 len:16; /*length of buffer data - 1*/
91 u64 pad[3]; /* For whatever reason, there needs to be 4 double-word offset */
93 char buf[METH_RX_BUFF_SIZE-sizeof(rx_status_vector)-3*sizeof(u64)-sizeof(u16)];/* data */
122 … /* Bits 8 through 14 are used to determine Inter-Packet Gap between "Back to Back" packets */
136 …2 /* Bits 12:14 of DMA control register indicate starting offset of packet data for RX operation */
137 #define METH_RX_DEPTH_SHIFT 4 /* Bits 8:4 define RX fifo depth -- when # of RX fifo entries != dept…
[all …]
/Linux-v6.1/drivers/i2c/busses/
Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
57 * @rx_msg: Current RX message
58 * @rx_pos: Position within current RX message
59 * @endianness: big/little-endian byte order
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Ddra72-evm-revc.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
5 #include "dra72-evm-common.dtsi"
6 #include "dra72x-mmc-iodelay.dtsi"
7 #include <dt-bindings/net/ti-dp83867.h>
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
30 compatible = "shared-dma-pool";
[all …]
Drk3xxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
[all …]
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dexynos5410.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 #include <dt-bindings/clock/exynos5410.h>
15 #include <dt-bindings/clock/exynos-audss-clk.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1600000000>;
42 compatible = "arm,cortex-a15";
[all …]
/Linux-v6.1/drivers/net/phy/
Ddp83867.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-consumer.h>
19 #include <dt-bindings/net/ti-dp83867.h>
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
198 mac = (const u8 *)ndev->dev_addr; in dp83867_set_wol()
201 return -EINVAL; in dp83867_set_wol()
215 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
217 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
[all …]
/Linux-v6.1/drivers/spi/
Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
23 #define CDNS_SPI_NAME "cdns-spi"
36 #define CDNS_SPI_THLD 0x28 /* Transmit FIFO Watermark Register,RW */
61 * SPI Configuration Register - Baud rate and slave select
80 #define CDNS_SPI_IXR_TXOW 0x00000004 /* SPI TX FIFO Overwater */
82 #define CDNS_SPI_IXR_RXNEMTY 0x00000010 /* SPI RX FIFO Not Empty */
100 * struct cdns_spi - This definition defines spi driver instance
106 * @rxbuf: Pointer to the RX buffer
[all …]
Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
17 #include <linux/spi/spi-mem.h>
21 #include "spi-dw.h"
30 u32 rx_sample_dly; /* RX sample delay */
64 snprintf(name, 32, "dw_spi%d", dws->master->bus_num); in dw_spi_debugfs_init()
65 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
66 if (!dws->debugfs) in dw_spi_debugfs_init()
67 return -ENOMEM; in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
[all …]

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