Lines Matching +full:rx +full:- +full:fifo +full:- +full:depth
1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
48 * struct xiic_i2c - Internal representation of the XIIC I2C bus
57 * @rx_msg: Current RX message
58 * @rx_pos: Position within current RX message
59 * @endianness: big/little-endian byte order
60 * @clk: Pointer to AXI4-lite input clock
91 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */
93 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
94 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
96 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
101 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
112 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
113 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
114 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
115 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
116 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
121 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
122 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
126 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
128 /* The following constants specify the depth of the FIFOs */
129 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
130 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
141 * Tx Fifo upper bit masks.
172 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
173 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
179 * For the register read and write functions, a little-endian and big-endian
183 * big-endian systems.
188 if (i2c->endianness == LITTLE) in xiic_setreg8()
189 iowrite8(value, i2c->base + reg); in xiic_setreg8()
191 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
198 if (i2c->endianness == LITTLE) in xiic_getreg8()
199 ret = ioread8(i2c->base + reg); in xiic_getreg8()
201 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
207 if (i2c->endianness == LITTLE) in xiic_setreg16()
208 iowrite16(value, i2c->base + reg); in xiic_setreg16()
210 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
215 if (i2c->endianness == LITTLE) in xiic_setreg32()
216 iowrite32(value, i2c->base + reg); in xiic_setreg32()
218 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
225 if (i2c->endianness == LITTLE) in xiic_getreg32()
226 ret = ioread32(i2c->base + reg); in xiic_getreg32()
228 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
270 dev_err(i2c->dev, "Failed to clear rx fifo\n"); in xiic_clear_rx_fifo()
271 return -ETIMEDOUT; in xiic_clear_rx_fifo()
284 /* Set receive Fifo depth to maximum (zero based). */ in xiic_reinit()
285 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
287 /* Reset Tx Fifo. */ in xiic_reinit()
290 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ in xiic_reinit()
293 /* make sure RX fifo is empty */ in xiic_reinit()
324 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
325 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", in xiic_read_rx()
334 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
339 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); in xiic_read_rx()
344 /* return the actual space left in the FIFO */ in xiic_tx_fifo_space()
345 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
355 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
358 while (len--) { in xiic_fill_tx_fifo()
359 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
361 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { in xiic_fill_tx_fifo()
362 /* last message in transfer -> STOP */ in xiic_fill_tx_fifo()
364 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
372 i2c->tx_msg = NULL; in xiic_wakeup()
373 i2c->rx_msg = NULL; in xiic_wakeup()
374 i2c->nmsgs = 0; in xiic_wakeup()
375 i2c->state = code; in xiic_wakeup()
376 complete(&i2c->completion); in xiic_wakeup()
394 mutex_lock(&i2c->lock); in xiic_process()
399 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
401 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
403 i2c->tx_msg, i2c->nmsgs); in xiic_process()
411 * Transmit error _OR_ RX completed in xiic_process()
416 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
424 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); in xiic_process()
426 if (i2c->rx_msg) { in xiic_process()
430 if (i2c->tx_msg) { in xiic_process()
436 /* Receive register/FIFO is full */ in xiic_process()
439 if (!i2c->rx_msg) { in xiic_process()
440 dev_dbg(i2c->adap.dev.parent, in xiic_process()
441 "%s unexpected RX IRQ\n", __func__); in xiic_process()
449 i2c->rx_msg = NULL; in xiic_process()
451 /* also clear TX error if there (RX complete) */ in xiic_process()
454 dev_dbg(i2c->adap.dev.parent, in xiic_process()
456 __func__, i2c->nmsgs); in xiic_process()
462 if (i2c->nmsgs > 1) { in xiic_process()
463 i2c->nmsgs--; in xiic_process()
464 i2c->tx_msg++; in xiic_process()
465 dev_dbg(i2c->adap.dev.parent, in xiic_process()
472 /* Transmit register/FIFO is empty or ½ empty */ in xiic_process()
477 if (!i2c->tx_msg) { in xiic_process()
478 dev_dbg(i2c->adap.dev.parent, in xiic_process()
485 /* current message sent and there is space in the fifo */ in xiic_process()
487 dev_dbg(i2c->adap.dev.parent, in xiic_process()
489 __func__, i2c->nmsgs); in xiic_process()
490 if (i2c->nmsgs > 1) { in xiic_process()
491 i2c->nmsgs--; in xiic_process()
492 i2c->tx_msg++; in xiic_process()
497 dev_dbg(i2c->adap.dev.parent, in xiic_process()
501 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) in xiic_process()
515 if (!i2c->tx_msg) in xiic_process()
520 if (i2c->nmsgs == 1 && !i2c->rx_msg && in xiic_process()
528 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
538 mutex_unlock(&i2c->lock); in xiic_process()
546 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; in xiic_bus_busy()
554 if (i2c->tx_msg || i2c->rx_msg) in xiic_busy()
555 return -EBUSY; in xiic_busy()
562 if (i2c->singlemaster) { in xiic_busy()
571 while (err && tries--) { in xiic_busy()
582 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
584 /* Clear and enable Rx full interrupt. */ in xiic_start_recv()
591 * we can check if ERROR and RX full is set at the same time in xiic_start_recv()
593 rx_watermark = msg->len; in xiic_start_recv()
596 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); in xiic_start_recv()
598 if (!(msg->flags & I2C_M_NOSTART)) in xiic_start_recv()
606 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); in xiic_start_recv()
608 if (i2c->nmsgs == 1) in xiic_start_recv()
613 i2c->tx_pos = msg->len; in xiic_start_recv()
618 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
620 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
621 __func__, msg, msg->len); in xiic_start_send()
622 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
626 if (!(msg->flags & I2C_M_NOSTART)) { in xiic_start_send()
630 if ((i2c->nmsgs == 1) && msg->len == 0) in xiic_start_send()
631 /* no data and last message -> add STOP */ in xiic_start_send()
640 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? in xiic_start_send()
650 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
651 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
653 if (!i2c->tx_msg) in __xiic_start_xfer()
656 i2c->rx_pos = 0; in __xiic_start_xfer()
657 i2c->tx_pos = 0; in __xiic_start_xfer()
658 i2c->state = STATE_START; in __xiic_start_xfer()
659 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
660 /* we dont date putting several reads in the FIFO */ in __xiic_start_xfer()
671 mutex_lock(&i2c->lock); in xiic_start_xfer()
677 i2c->tx_msg = msgs; in xiic_start_xfer()
678 i2c->rx_msg = NULL; in xiic_start_xfer()
679 i2c->nmsgs = num; in xiic_start_xfer()
680 init_completion(&i2c->completion); in xiic_start_xfer()
687 mutex_unlock(&i2c->lock); in xiic_start_xfer()
697 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, in xiic_xfer()
700 err = pm_runtime_resume_and_get(i2c->dev); in xiic_xfer()
706 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); in xiic_xfer()
710 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); in xiic_xfer()
711 mutex_lock(&i2c->lock); in xiic_xfer()
713 i2c->tx_msg = NULL; in xiic_xfer()
714 i2c->rx_msg = NULL; in xiic_xfer()
715 i2c->nmsgs = 0; in xiic_xfer()
716 err = -ETIMEDOUT; in xiic_xfer()
718 i2c->tx_msg = NULL; in xiic_xfer()
719 i2c->rx_msg = NULL; in xiic_xfer()
720 i2c->nmsgs = 0; in xiic_xfer()
722 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
724 mutex_unlock(&i2c->lock); in xiic_xfer()
725 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
726 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
760 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
762 return -ENOMEM; in xiic_i2c_probe()
765 i2c->base = devm_ioremap_resource(&pdev->dev, res); in xiic_i2c_probe()
766 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
767 return PTR_ERR(i2c->base); in xiic_i2c_probe()
773 pdata = dev_get_platdata(&pdev->dev); in xiic_i2c_probe()
777 i2c->adap = xiic_adapter; in xiic_i2c_probe()
778 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
779 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
780 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
781 snprintf(i2c->adap.name, sizeof(i2c->adap.name), in xiic_i2c_probe()
782 DRIVER_NAME " %s", pdev->name); in xiic_i2c_probe()
784 mutex_init(&i2c->lock); in xiic_i2c_probe()
786 i2c->clk = devm_clk_get(&pdev->dev, NULL); in xiic_i2c_probe()
787 if (IS_ERR(i2c->clk)) in xiic_i2c_probe()
788 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), in xiic_i2c_probe()
791 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_probe()
793 dev_err(&pdev->dev, "Unable to enable clock.\n"); in xiic_i2c_probe()
796 i2c->dev = &pdev->dev; in xiic_i2c_probe()
797 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
798 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
799 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
800 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
801 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, in xiic_i2c_probe()
803 pdev->name, i2c); in xiic_i2c_probe()
806 dev_err(&pdev->dev, "Cannot claim IRQ\n"); in xiic_i2c_probe()
810 i2c->singlemaster = in xiic_i2c_probe()
811 of_property_read_bool(pdev->dev.of_node, "single-master"); in xiic_i2c_probe()
815 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not in xiic_i2c_probe()
818 i2c->endianness = LITTLE; in xiic_i2c_probe()
823 i2c->endianness = BIG; in xiic_i2c_probe()
827 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); in xiic_i2c_probe()
832 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
840 for (i = 0; i < pdata->num_devices; i++) in xiic_i2c_probe()
841 i2c_new_client_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
847 pm_runtime_set_suspended(&pdev->dev); in xiic_i2c_probe()
848 pm_runtime_disable(&pdev->dev); in xiic_i2c_probe()
849 clk_disable_unprepare(i2c->clk); in xiic_i2c_probe()
859 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
861 ret = pm_runtime_resume_and_get(i2c->dev); in xiic_i2c_remove()
866 pm_runtime_put_sync(i2c->dev); in xiic_i2c_remove()
867 clk_disable_unprepare(i2c->clk); in xiic_i2c_remove()
868 pm_runtime_disable(&pdev->dev); in xiic_i2c_remove()
869 pm_runtime_set_suspended(&pdev->dev); in xiic_i2c_remove()
870 pm_runtime_dont_use_autosuspend(&pdev->dev); in xiic_i2c_remove()
877 { .compatible = "xlnx,xps-iic-2.00.a", },
887 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
897 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
924 MODULE_AUTHOR("info@mocean-labs.com");