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/Linux-v5.15/arch/arm/mach-ep93xx/
Dclock.c29 unsigned long rate; member
36 int (*set_rate)(struct clk *clk, unsigned long rate);
42 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
43 static int set_div_rate(struct clk *clk, unsigned long rate);
44 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
45 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
48 .rate = EP93XX_EXT_CLK_RATE,
107 .rate = EP93XX_EXT_CLK_RATE,
111 .rate = EP93XX_EXT_CLK_RATE,
312 unsigned long rate = clk_get_rate(clk->parent); in get_uart_rate() local
[all …]
/Linux-v5.15/drivers/clk/rockchip/
Dclk-pll.c51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
57 if (rate == rate_table[i].rate) in rockchip_get_pll_settings()
73 if (drate >= rate_table[i].rate) in rockchip_pll_round_rate()
74 return rate_table[i].rate; in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
140 struct rockchip_pll_rate_table *rate) in rockchip_rk3036_pll_get_params() argument
145 rate->fbdiv = ((pllcon >> RK3036_PLLCON0_FBDIV_SHIFT) in rockchip_rk3036_pll_get_params()
147 rate->postdiv1 = ((pllcon >> RK3036_PLLCON0_POSTDIV1_SHIFT) in rockchip_rk3036_pll_get_params()
151 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
153 rate->postdiv2 = ((pllcon >> RK3036_PLLCON1_POSTDIV2_SHIFT) in rockchip_rk3036_pll_get_params()
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/Linux-v5.15/drivers/mmc/host/
Dsdhci-of-aspeed-test.c8 int rate = 52000000; in aspeed_sdhci_phase_ddr52() local
11 aspeed_sdhci_phase_to_tap(NULL, rate, 0)); in aspeed_sdhci_phase_ddr52()
13 aspeed_sdhci_phase_to_tap(NULL, rate, 1)); in aspeed_sdhci_phase_ddr52()
15 aspeed_sdhci_phase_to_tap(NULL, rate, 2)); in aspeed_sdhci_phase_ddr52()
17 aspeed_sdhci_phase_to_tap(NULL, rate, 3)); in aspeed_sdhci_phase_ddr52()
19 aspeed_sdhci_phase_to_tap(NULL, rate, 4)); in aspeed_sdhci_phase_ddr52()
21 aspeed_sdhci_phase_to_tap(NULL, rate, 5)); in aspeed_sdhci_phase_ddr52()
23 aspeed_sdhci_phase_to_tap(NULL, rate, 23)); in aspeed_sdhci_phase_ddr52()
25 aspeed_sdhci_phase_to_tap(NULL, rate, 24)); in aspeed_sdhci_phase_ddr52()
27 aspeed_sdhci_phase_to_tap(NULL, rate, 25)); in aspeed_sdhci_phase_ddr52()
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/Linux-v5.15/drivers/clk/sunxi-ng/
Dccu_nm.c22 u64 rate = parent; in ccu_nm_calc_rate() local
24 rate *= n; in ccu_nm_calc_rate()
25 do_div(rate, m); in ccu_nm_calc_rate()
27 return rate; in ccu_nm_calc_rate()
30 static void ccu_nm_find_best(unsigned long parent, unsigned long rate, in ccu_nm_find_best() argument
42 if (tmp_rate > rate) in ccu_nm_find_best()
45 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_nm_find_best()
82 unsigned long rate; in ccu_nm_recalc_rate() local
87 rate = ccu_frac_helper_read_rate(&nm->common, &nm->frac); in ccu_nm_recalc_rate()
90 rate /= nm->fixed_post_div; in ccu_nm_recalc_rate()
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Dccu_mp.c13 static void ccu_mp_find_best(unsigned long parent, unsigned long rate, in ccu_mp_find_best() argument
25 if (tmp_rate > rate) in ccu_mp_find_best()
28 if ((rate - tmp_rate) < (rate - best_rate)) { in ccu_mp_find_best()
42 unsigned long rate, in ccu_mp_find_best_with_parent_adj() argument
56 * unsigned long in rate * m * p below in ccu_mp_find_best_with_parent_adj()
59 maxdiv = min(ULONG_MAX / rate, maxdiv); in ccu_mp_find_best_with_parent_adj()
68 if (rate * div == parent_rate_saved) { in ccu_mp_find_best_with_parent_adj()
71 * rate can be divided from parent clock without in ccu_mp_find_best_with_parent_adj()
72 * needing to change parent rate, so return the in ccu_mp_find_best_with_parent_adj()
76 return rate; in ccu_mp_find_best_with_parent_adj()
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/Linux-v5.15/tools/testing/selftests/tc-testing/tc-tests/actions/
Dpolice.json17 "cmdUnderTest": "$TC actions add action police rate 1kbit burst 10k index 1",
20 "matchPattern": "action order [0-9]*: police 0x1 rate 1Kbit burst 10Kb",
40 "$TC actions add action police rate 4Mbit burst 120k index 9"
42 "cmdUnderTest": "$TC actions add action police rate 8kbit burst 24k index 9",
66 "cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 1k index 98",
69 "matchPattern": "action order [0-9]*: police 0x62 rate 90Kbit burst 10Kb mtu 1Kb",
90 …"cmdUnderTest": "$TC actions add action police rate 90kbit burst 10k mtu 2kb peakrate 100kbit inde…
93 …"matchPattern": "action order [0-9]*: police 0x3 rate 90Kbit burst 10Kb mtu 2Kb peakrate 100Kbit",
114 … "cmdUnderTest": "$TC actions add action police rate 5kbit burst 6kb peakrate 10kbit index 9",
117 "matchPattern": "action order [0-9]*: police 0x9 rate 5Kb burst 10Kb",
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Dsample.json17 "cmdUnderTest": "$TC actions add action sample rate 10 group 1 index 2",
20 "matchPattern": "action order [0-9]+: sample rate 1/10 group 1.*index 2 ref",
41 "cmdUnderTest": "$TC actions add action sample rate 700 group 2 continue index 2",
44 "matchPattern": "action order [0-9]+: sample rate 1/700 group 2 continue.*index 2 ref",
65 "cmdUnderTest": "$TC actions add action sample rate 10000 group 11 drop index 22",
68 "matchPattern": "action order [0-9]+: sample rate 1/10000 group 11 drop.*index 22 ref",
89 "cmdUnderTest": "$TC actions add action sample rate 20000 group 72 reclassify index 100",
92 … "matchPattern": "action order [0-9]+: sample rate 1/20000 group 72 reclassify.*index 100 ref",
113 "cmdUnderTest": "$TC actions add action sample rate 20 group 2 pipe index 100",
116 "matchPattern": "action order [0-9]+: sample rate 1/20 group 2 pipe.*index 100 ref",
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/Linux-v5.15/tools/testing/selftests/drivers/net/mlxsw/
Ddevlink_trap_policer.sh144 devlink trap policer set $DEVLINK_DEV policer 1 rate 0 &> /dev/null
145 check_fail $? "Policer rate was changed to rate lower than limit"
147 rate 2000000001 &> /dev/null
148 check_fail $? "Policer rate was changed to rate higher than limit"
150 devlink trap policer set $DEVLINK_DEV policer 1 rate 1
151 check_err $? "Failed to set policer rate to minimum"
152 devlink trap policer set $DEVLINK_DEV policer 1 rate 2000000000
153 check_err $? "Failed to set policer rate to maximum"
155 log_test "Trap policer rate limits"
205 local rate pct drop_rate
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/Linux-v5.15/drivers/net/wireless/intel/iwlwifi/mvm/
Drs.c77 * rate, ht rate, prev rate, next rate
79 * If there isn't a valid next or previous rate then INV is used which
121 struct rs_rate *rate,
133 struct rs_rate *rate, in rs_ant_allow() argument
140 struct rs_rate *rate, in rs_mimo_allow() argument
162 struct rs_rate *rate, in rs_siso_allow() argument
172 struct rs_rate *rate, in rs_sgi_allow() argument
178 if (is_ht20(rate) && (ht_cap->cap & in rs_sgi_allow()
181 if (is_ht40(rate) && (ht_cap->cap & in rs_sgi_allow()
184 if (is_ht80(rate) && (vht_cap->cap & in rs_sgi_allow()
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Drs.h33 u8 prev_rs; /* previous rate used in rs algo */
34 u8 next_rs; /* next rate used in rs algo */
195 #define is_legacy(rate) is_type_legacy((rate)->type) argument
196 #define is_ht_siso(rate) is_type_ht_siso((rate)->type) argument
197 #define is_ht_mimo2(rate) is_type_ht_mimo2((rate)->type) argument
198 #define is_vht_siso(rate) is_type_vht_siso((rate)->type) argument
199 #define is_vht_mimo2(rate) is_type_vht_mimo2((rate)->type) argument
200 #define is_siso(rate) is_type_siso((rate)->type) argument
201 #define is_mimo2(rate) is_type_mimo2((rate)->type) argument
202 #define is_mimo(rate) is_type_mimo((rate)->type) argument
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/Linux-v5.15/drivers/clk/at91/
Dclk-audio-pll.c10 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
11 * its own parent. PMC and PAD can then divide the FRAC rate to best match the
12 * asked rate.
16 * rate - rate is adjustable.
17 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
22 * rate - rate is adjustable.
23 * clk->rate = parent->rate / (qdpmc + 1)
28 * rate - rate is adjustable.
29 * clk->rate = parent->rate / (qdaudio * div))
216 static int clk_audio_pll_frac_compute_frac(unsigned long rate, in clk_audio_pll_frac_compute_frac() argument
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/Linux-v5.15/drivers/clk/ti/
Ddpll44xx.c34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
105 * @hw: pointer to the clock to compute the rate for
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
118 unsigned long rate; in omap4_dpll_regm4xen_recalc() local
126 rate = omap2_get_dpll_rate(clk); in omap4_dpll_regm4xen_recalc()
131 rate *= OMAP4430_REGM4XEN_MULT; in omap4_dpll_regm4xen_recalc()
133 return rate; in omap4_dpll_regm4xen_recalc()
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/Linux-v5.15/drivers/clk/samsung/
Dclk-pll.c39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
45 if (rate == rate_table[i].rate) in samsung_get_pll_settings()
61 if (drate >= rate_table[i].rate) in samsung_pll_round_rate()
62 return rate_table[i].rate; in samsung_pll_round_rate()
66 return rate_table[i - 1].rate; in samsung_pll_round_rate()
238 const struct samsung_pll_rate_table *rate, u32 pll_con) in samsung_pll35xx_mp_change() argument
245 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
252 const struct samsung_pll_rate_table *rate; in samsung_pll35xx_set_rate() local
255 /* Get required rate settings from table */ in samsung_pll35xx_set_rate()
256 rate = samsung_get_pll_settings(pll, drate); in samsung_pll35xx_set_rate()
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/Linux-v5.15/drivers/net/wireless/realtek/rtw88/
Dutil.c82 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss) in rtw_desc_to_mcsrate() argument
84 if (rate <= DESC_RATE54M) in rtw_desc_to_mcsrate()
87 if (rate >= DESC_RATEVHT1SS_MCS0 && in rtw_desc_to_mcsrate()
88 rate <= DESC_RATEVHT1SS_MCS9) { in rtw_desc_to_mcsrate()
90 *mcs = rate - DESC_RATEVHT1SS_MCS0; in rtw_desc_to_mcsrate()
91 } else if (rate >= DESC_RATEVHT2SS_MCS0 && in rtw_desc_to_mcsrate()
92 rate <= DESC_RATEVHT2SS_MCS9) { in rtw_desc_to_mcsrate()
94 *mcs = rate - DESC_RATEVHT2SS_MCS0; in rtw_desc_to_mcsrate()
95 } else if (rate >= DESC_RATEVHT3SS_MCS0 && in rtw_desc_to_mcsrate()
96 rate <= DESC_RATEVHT3SS_MCS9) { in rtw_desc_to_mcsrate()
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Dphy.c1085 u32 addr, u32 mask, u32 val, u8 *rate, in rtw_phy_get_rate_values_of_txpwr_by_rate() argument
1093 rate[0] = DESC_RATE6M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1094 rate[1] = DESC_RATE9M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1095 rate[2] = DESC_RATE12M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1096 rate[3] = DESC_RATE18M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1103 rate[0] = DESC_RATE24M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1104 rate[1] = DESC_RATE36M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1105 rate[2] = DESC_RATE48M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1106 rate[3] = DESC_RATE54M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
1112 rate[0] = DESC_RATE1M; in rtw_phy_get_rate_values_of_txpwr_by_rate()
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/Linux-v5.15/drivers/net/wireless/realtek/rtlwifi/
Drc.c9 *Finds the highest rate index we can use
11 *it to lowest rate CCK_1M, otherwise we set rate to
12 *highest rate based on wireless mode used for iwconfig
13 *show Tx rate.
24 struct ieee80211_tx_rate rate; in _rtl_rc_get_highest_rix() local
42 *this rate is no use for true rate, firmware in _rtl_rc_get_highest_rix()
43 *will control rate at all it just used for in _rtl_rc_get_highest_rix()
45 *2.in rtl_get_tcb_desc when we check rate is in _rtl_rc_get_highest_rix()
46 * 1M we will not use FW rate but user rate. in _rtl_rc_get_highest_rix()
70 ieee80211_rate_set_vht(&rate, in _rtl_rc_get_highest_rix()
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/Linux-v5.15/drivers/memory/tegra/
Dtegra20-emc.c160 unsigned long rate; member
196 * a min/max clock rate, these rates are contained in this array.
200 /* protect shared rate-change code path */
228 unsigned long rate) in tegra_emc_find_timing() argument
234 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
241 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
248 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
250 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change()
256 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
257 __func__, timing->rate, rate); in emc_prepare_timing_change()
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/Linux-v5.15/arch/arm/mach-omap1/
Dclock.c54 return clk->parent->rate / div; in omap1_sossi_recalc()
132 static int calc_dsor_exp(struct clk *clk, unsigned long rate) in calc_dsor_exp() argument
153 realrate = parent->rate; in calc_dsor_exp()
155 if (realrate <= rate) in calc_dsor_exp()
169 return clk->parent->rate / dsor; in omap1_ckctl_recalc()
187 return clk->parent->rate / dsor; in omap1_ckctl_recalc_dsp_domain()
191 int omap1_select_table_rate(struct clk *clk, unsigned long rate) in omap1_select_table_rate() argument
193 /* Find the highest supported frequency <= rate and switch to it */ in omap1_select_table_rate()
197 ref_rate = ck_ref_p->rate; in omap1_select_table_rate()
199 for (ptr = omap1_rate_table; ptr->rate; ptr++) { in omap1_select_table_rate()
[all …]
/Linux-v5.15/drivers/clk/tegra/
Dclk-tegra124-emc.c66 unsigned long rate, parent_rate; member
101 * so get the parent rate explicitly. in emc_recalc_rate()
112 * Rounds up unless no higher rate exists, in which case down. This way is
113 * safer since things have EMC rate floors. Also don't touch parent_rate
138 if (timing->rate < req->rate && i != t - 1) in emc_determine_rate()
141 if (timing->rate > req->max_rate) { in emc_determine_rate()
143 req->rate = tegra->timings[i - 1].rate; in emc_determine_rate()
147 if (timing->rate < req->min_rate) in emc_determine_rate()
150 req->rate = timing->rate; in emc_determine_rate()
155 req->rate = timing->rate; in emc_determine_rate()
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dclkt2xxx_virt_prcm_set.c16 * code. However, some notion of "rate set" is probably still necessary
17 * for OMAP2xxx at least. Rate sets should be generalized so they can be
19 * has in the past expressed a preference to use rate sets for OPP changes,
46 * sys_ck_rate: the rate of the external high-frequency clock
56 * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set.
65 * Look for a rate equal or less than the target rate given a configuration set.
71 long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_round_to_table_rate() argument
88 if (ptr->mpu_speed <= rate) in omap2_round_to_table_rate()
94 /* Sets basic clocks based on the specified rate */
95 int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, in omap2_select_table_rate() argument
[all …]
/Linux-v5.15/drivers/clk/
Dclk-vt8500.c131 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, in vt8500_dclk_round_rate() argument
137 if (rate == 0) in vt8500_dclk_round_rate()
140 divisor = *prate / rate; in vt8500_dclk_round_rate()
142 /* If prate / rate would be decimal, incr the divisor */ in vt8500_dclk_round_rate()
143 if (rate * divisor < *prate) in vt8500_dclk_round_rate()
157 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate, in vt8500_dclk_set_rate() argument
164 if (rate == 0) in vt8500_dclk_set_rate()
167 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
350 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
356 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
[all …]
/Linux-v5.15/drivers/clk/imx/
Dclk-pllv3.c39 * @ref_clock: reference clock rate
119 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_round_rate() argument
124 return (rate >= parent_rate * 22) ? parent_rate * 22 : in clk_pllv3_round_rate()
128 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_set_rate() argument
134 if (rate == parent_rate * 22) in clk_pllv3_set_rate()
136 else if (rate == parent_rate * 20) in clk_pllv3_set_rate()
167 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv3_sys_round_rate() argument
175 if (rate > max_rate) in clk_pllv3_sys_round_rate()
176 rate = max_rate; in clk_pllv3_sys_round_rate()
177 else if (rate < min_rate) in clk_pllv3_sys_round_rate()
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Dclk-scu.c56 u32 rate; member
76 * struct imx_sc_msg_req_set_clock_rate - clock set rate protocol
78 * @rate: rate to set
79 * @resource: clock resource to set rate
82 * This structure describes the SCU protocol of clock rate set
86 __le32 rate; member
97 __le32 rate; member
101 * struct imx_sc_msg_get_clock_rate - clock get rate protocol
103 * @req: get rate request protocol
104 * @resp: get rate response protocol
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/Linux-v5.15/drivers/staging/rtl8723bs/include/
Dhal_com.h21 /* Rate */
49 #define HDATA_RATE(rate)\ argument
50 (rate == DESC_RATE1M) ? "CCK_1M" : \
51 (rate == DESC_RATE2M) ? "CCK_2M" : \
52 (rate == DESC_RATE5_5M) ? "CCK5_5M" : \
53 (rate == DESC_RATE11M) ? "CCK_11M" : \
54 (rate == DESC_RATE6M) ? "OFDM_6M" : \
55 (rate == DESC_RATE9M) ? "OFDM_9M" : \
56 (rate == DESC_RATE12M) ? "OFDM_12M" : \
57 (rate == DESC_RATE18M) ? "OFDM_18M" : \
[all …]
/Linux-v5.15/drivers/clk/qcom/
Dclk-rcg2.c141 * Calculate m/n:d rate
144 * rate = ----------- x ---
148 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) in calc_rate() argument
151 rate *= 2; in calc_rate()
152 rate /= hid_div + 1; in calc_rate()
156 u64 tmp = rate; in calc_rate()
159 rate = tmp; in calc_rate()
162 return rate; in calc_rate()
196 unsigned long clk_flags, rate = req->rate; in _freq_tbl_determine_rate() local
203 f = qcom_find_freq_floor(f, rate); in _freq_tbl_determine_rate()
[all …]

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