Searched +full:r9a06g032 +full:- +full:sysctrl (Results 1 – 12 of 12) sorted by relevance
/Linux-v6.1/arch/arm/boot/dts/ |
D | r9a06g032.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 18 #address-cells = <1>; 19 #size-cells = <0>; 23 compatible = "arm,cortex-a7"; [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/clock/ |
D | renesas,r9a06g032-sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas RZ/N1D (R9A06G032) System Controller 10 - Gareth Williams <gareth.williams.jx@renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 15 const: renesas,r9a06g032-sysctrl 23 - description: External 40 MHz crystal 24 - description: Optional external 32.768 kHz crystal [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/mtd/ |
D | renesas-nandc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/renesas-nandc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car Gen3 & RZ/N1x NAND flash controller 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 - $ref: "nand-controller.yaml" 18 - items: 19 - enum: 20 - renesas,r9a06g032-nandc [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/rtc/ |
D | renesas,rzn1-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas RZ/N1 SoCs Real-Time Clock DT bindings 10 - Miquel Raynal <miquel.raynal@bootlin.com> 13 - $ref: rtc.yaml# 18 - enum: 19 - renesas,r9a06g032-rtc 20 - const: renesas,rzn1-rtc [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/net/pcs/ |
D | renesas,rzn1-miic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Clément Léger <clement.leger@bootlin.com> 17 '#address-cells': 20 '#size-cells': 25 - enum: 26 - renesas,r9a06g032-miic 27 - const: renesas,rzn1-miic [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/net/dsa/ |
D | renesas,rzn1-a5psw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Clément Léger <clement.leger@bootlin.com> 17 - $ref: dsa.yaml# 22 - enum: 23 - renesas,r9a06g032-a5psw 24 - const: renesas,rzn1-a5psw 31 - description: Device Level Ring (DLR) interrupt [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/net/can/ |
D | nxp,sja1000.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Wolfgang Grandegger <wg@grandegger.com> 15 - enum: 16 - nxp,sja1000 17 - technologic,sja1000 18 - items: 19 - enum: 20 - renesas,r9a06g032-sja1000 # RZ/N1D [all …]
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/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/ |
D | renesas,rzn1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gareth Williams <gareth.williams.jx@renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 16 - enum: 17 - renesas,r9a06g032-pinctrl # RZ/N1D 18 - renesas,r9a06g033-pinctrl # RZ/N1S 19 - const: renesas,rzn1-pinctrl # Generic RZ/N1 [all …]
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/Linux-v6.1/drivers/soc/renesas/ |
D | r9a06g032-smp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R9A06G032 Second CA7 enabler. 8 * Derived from actions,s500-smp 18 * writing an address into the BOOTADDR register of sysctrl. 20 * So the default value of the "cpu-release-addr" corresponds to BOOTADDR... 25 * So for NONSEC mode, the bootloader re-parks the second CPU into a pen 26 * in SRAM, and changes the "cpu-release-addr" of linux's DT to a SRAM address, 39 return -ENODEV; in r9a06g032_smp_boot_secondary() 54 int ret = -EINVAL, dns; in r9a06g032_smp_prepare_cpus() 67 if (of_find_property(dn, "cpu-release-addr", &dns)) { in r9a06g032_smp_prepare_cpus() [all …]
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/Linux-v6.1/drivers/clk/renesas/ |
D | r9a06g032-clocks.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R9A06G032 clock driver 11 #include <linux/clk-provider.h> 24 #include <linux/soc/renesas/r9a06g032-sysctrl.h> 26 #include <dt-bindings/clock/r9a06g032-sysctrl.h> 50 /* For fixed-factor ones */ 329 return -EPROBE_DEFER; in r9a06g032_sysctrl_set_dmamux() 331 spin_lock_irqsave(&sysctrl_priv->lock, flags); in r9a06g032_sysctrl_set_dmamux() 333 dmamux = readl(sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); in r9a06g032_sysctrl_set_dmamux() 336 writel(dmamux, sysctrl_priv->reg + R9A06G032_SYSCTRL_DMAMUX); in r9a06g032_sysctrl_set_dmamux() [all …]
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/Linux-v6.1/include/dt-bindings/clock/ |
D | r9a06g032-sysctrl.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * R9A06G032 sysctrl IDs
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/Linux-v6.1/drivers/dma/dw/ |
D | rzn1-dmamux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2022 Schneider-Electric 11 #include <linux/soc/renesas/r9a06g032-sysctrl.h> 32 dev_dbg(dev, "Unmapping DMAMUX request %u\n", map->req_idx); in rzn1_dmamux_free() 34 clear_bit(map->req_idx, dmamux->used_chans); in rzn1_dmamux_free() 42 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in rzn1_dmamux_route_allocate() 49 if (dma_spec->args_count != RNZ1_DMAMUX_NCELLS) in rzn1_dmamux_route_allocate() 50 return ERR_PTR(-EINVAL); in rzn1_dmamux_route_allocate() 54 return ERR_PTR(-ENOMEM); in rzn1_dmamux_route_allocate() 56 chan = dma_spec->args[0]; in rzn1_dmamux_route_allocate() [all …]
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