| /Linux-v6.1/drivers/spi/ |
| D | spi-bcm-qspi.c | 25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi) in has_bspi() argument
257 return qspi->bspi_mode; in has_bspi()
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi) in bcm_qspi_has_fastbr() argument
263 if (!has_bspi(qspi) && in bcm_qspi_has_fastbr()
264 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_fastbr()
265 (qspi->mspi_min_rev >= 5))) in bcm_qspi_has_fastbr()
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi) in bcm_qspi_has_sysclk_108() argument
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk || in bcm_qspi_has_sysclk_108()
275 ((qspi->mspi_maj_rev >= 1) && in bcm_qspi_has_sysclk_108()
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| D | spi-ti-qspi.c | 3 * TI QSPI driver
127 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, in ti_qspi_read() argument
130 return readl(qspi->base + reg); in ti_qspi_read()
133 static inline void ti_qspi_write(struct ti_qspi *qspi, in ti_qspi_write() argument
136 writel(val, qspi->base + reg); in ti_qspi_write()
141 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); in ti_qspi_setup() local
145 dev_dbg(qspi->dev, "master busy doing other transfers\n"); in ti_qspi_setup()
149 if (!qspi->master->max_speed_hz) { in ti_qspi_setup()
150 dev_err(qspi->dev, "spi max frequency not defined\n"); in ti_qspi_setup()
154 spi->max_speed_hz = min(spi->max_speed_hz, qspi->master->max_speed_hz); in ti_qspi_setup()
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| D | spi-stm32-qspi.c | 132 struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; in stm32_qspi_irq() local
135 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
136 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
141 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
142 complete(&qspi->match_completion); in stm32_qspi_irq()
150 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
151 complete(&qspi->data_completion); in stm32_qspi_irq()
167 static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, in stm32_qspi_tx_poll() argument
185 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
189 dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", in stm32_qspi_tx_poll()
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| D | spi-microchip-core-qspi.c | 3 * Microchip coreQSPI QSPI controller driver
25 * QSPI Control register mask defines
43 * QSPI Frames register mask defines
55 * QSPI Interrupt Enable register mask defines
65 * QSPI Status register mask defines
84 /* QSPI ready time out value */
88 * QSPI Register offsets.
103 * struct mchp_coreqspi - Defines qspi driver instance
104 * @regs: Virtual address of the QSPI controller registers
105 * @clk: QSPI Operating clock
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| D | spi-zynq-qspi.c | 41 * QSPI Configuration Register bit Masks
44 * of the QSPI controller
57 * QSPI Configuration Register - Baud rate and slave select
67 * QSPI Interrupt Registers bit Masks
72 #define ZYNQ_QSPI_IXR_RX_OVERFLOW_MASK BIT(0) /* QSPI RX FIFO Overflow */
73 #define ZYNQ_QSPI_IXR_TXNFULL_MASK BIT(2) /* QSPI TX FIFO Overflow */
74 #define ZYNQ_QSPI_IXR_TXFULL_MASK BIT(3) /* QSPI TX FIFO is full */
75 #define ZYNQ_QSPI_IXR_RXNEMTY_MASK BIT(4) /* QSPI RX FIFO Not Empty */
76 #define ZYNQ_QSPI_IXR_RXF_FULL_MASK BIT(5) /* QSPI RX FIFO is full */
77 #define ZYNQ_QSPI_IXR_TXF_UNDRFLOW_MASK BIT(6) /* QSPI TX FIFO Underflow */
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| D | spi-zynqmp-gqspi.c | 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
26 /* Generic QSPI register offsets */
143 * struct zynqmp_qspi - Defines qspi driver instance
144 * @regs: Virtual address of the QSPI controller registers
158 * @mode: Defines the mode in which QSPI is operating
256 * The default settings of the QSPI controller's configurable parameters on
268 * - Enable the QSPI controller
356 * @qspi: Pointer to the spi_device structure
359 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) in zynqmp_qspi_chipselect() argument
361 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); in zynqmp_qspi_chipselect()
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| D | Makefile | 33 obj-$(CONFIG_SPI_BCM_QSPI) += spi-iproc-qspi.o spi-brcmstb-qspi.o spi-bcm-qspi.o
40 obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
57 obj-$(CONFIG_SPI_FSL_QUADSPI) += spi-fsl-qspi.o
76 obj-$(CONFIG_SPI_MICROCHIP_CORE_QSPI) += spi-microchip-core-qspi.o
95 obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o
105 obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
126 obj-$(CONFIG_SPI_STM32_QSPI) += spi-stm32-qspi.o
145 obj-$(CONFIG_SPI_ZYNQ_QSPI) += spi-zynq-qspi.o
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| D | Kconfig | 237 Cadence QSPI is a specialized controller for connecting an SPI
239 device with a Cadence QSPI controller and want to access the
262 tristate "Freescale Coldfire QSPI controller"
265 This enables support for the Coldfire QSPI controller in master
364 tristate "Freescale QSPI controller"
595 tristate "Microchip FPGA QSPI controllers"
598 This enables the QSPI driver for Microchip FPGA QSPI controllers.
599 Say Y or M here if you want to use the QSPI controllers on
601 If built as a module, it will be called spi-microchip-core-qspi.
693 tristate "DRA7xxx QSPI controller support"
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| D | atmel-quadspi.c | 3 * Driver for Atmel QSPI Controller
27 /* QSPI register offsets */
359 /* offset of the data access in the QSPI memory space */ in atmel_qspi_set_cfg()
375 * If the QSPI controller is set in regular SPI mode, set it in in atmel_qspi_set_cfg()
386 /* Set QSPI Instruction Frame registers. */ in atmel_qspi_set_cfg()
495 /* Compute the QSPI baudrate */ in atmel_qspi_setup()
515 /* Reset the QSPI controller */ in atmel_qspi_init()
518 /* Set the QSPI controller by default in Serial Memory Mode */ in atmel_qspi_init()
522 /* Enable the QSPI controller */ in atmel_qspi_init()
606 dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); in atmel_qspi_probe()
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| /Linux-v6.1/Documentation/devicetree/bindings/spi/ |
| D | ti_qspi.txt | 1 TI QSPI controller.
4 - compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
5 - reg: Should contain QSPI registers location and length.
7 - qspi_base: Qspi configuration register Address space
10 - interrupts: should contain the qspi interrupt number.
12 - ti,hwmods: Name of the hwmod associated to the QSPI
19 - syscon-chipselects: Handle to system control region contains QSPI
22 NOTE: TI QSPI controller requires different pinmux and IODelay
26 specified in the slave nodes of TI QSPI controller without appropriate
32 qspi: qspi@47900000 {
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| D | fsl,spi-fsl-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/fsl,spi-fsl-qspi.yaml#
19 - fsl,vf610-qspi
20 - fsl,imx6sx-qspi
21 - fsl,imx7d-qspi
22 - fsl,imx6ul-qspi
23 - fsl,ls1021a-qspi
24 - fsl,ls2080a-qspi
27 - fsl,ls1043a-qspi
28 - const: fsl,ls1021a-qspi
31 - fsl,imx8mq-qspi
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| D | cdns,qspi-nor.yaml | 4 $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
28 - ti,k2g-qspi
30 - intel,lgm-qspi
32 - intel,socfpga-qspi
33 - const: cdns,qspi-nor
34 - const: cdns,qspi-nor
74 Flag to indicate that QSPI return clock is used to latch the read
75 data rather than the QSPI clock. Make sure that QSPI return clock
88 enum: [ qspi, qspi-ocp ]
105 qspi: spi@ff705000 {
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| D | qcom,spi-qcom-qspi.yaml | 5 $id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
8 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
13 description: The QSPI controller allows SPI protocol communication in single,
24 - qcom,sc7180-qspi
25 - qcom,sc7280-qspi
26 - qcom,sdm845-qspi
28 - const: qcom,qspi-v1
44 - description: QSPI core clock
53 - const: qspi-config
54 - const: qspi-memory
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| D | renesas,rspi.yaml | 7 title: Renesas (Quad) Serial Peripheral Interface (RSPI/QSPI)
31 - renesas,qspi-r8a7742 # RZ/G1H
32 - renesas,qspi-r8a7743 # RZ/G1M
33 - renesas,qspi-r8a7744 # RZ/G1N
34 - renesas,qspi-r8a7745 # RZ/G1E
35 - renesas,qspi-r8a77470 # RZ/G1C
36 - renesas,qspi-r8a7790 # R-Car H2
37 - renesas,qspi-r8a7791 # R-Car M2-W
38 - renesas,qspi-r8a7792 # R-Car V2H
39 - renesas,qspi-r8a7793 # R-Car M2-N
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| D | brcm,spi-bcm-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
36 - brcm,spi-bcm7425-qspi
37 - brcm,spi-bcm7429-qspi
38 - brcm,spi-bcm7435-qspi
39 - brcm,spi-bcm7445-qspi
40 - brcm,spi-bcm7216-qspi
41 - brcm,spi-bcm7278-qspi
42 - const: brcm,spi-bcm-qspi
47 - brcm,spi-brcmstb-qspi
49 - brcm,spi-nsp-qspi
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| D | nvidia,tegra210-quad.yaml | 19 - nvidia,tegra210-qspi
20 - nvidia,tegra186-qspi
21 - nvidia,tegra194-qspi
22 - nvidia,tegra234-qspi
23 - nvidia,tegra241-qspi
33 - const: qspi
77 compatible = "nvidia,tegra210-qspi";
84 clock-names = "qspi", "qspi_out";
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| D | st,stm32-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml#
7 title: STMicroelectronics STM32 Quad Serial Peripheral Interface (QSPI) bindings
18 const: st,stm32f469-qspi
27 - const: qspi
64 compatible = "st,stm32f469-qspi";
66 reg-names = "qspi", "qspi_mm";
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| D | xlnx,zynq-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/xlnx,zynq-qspi.yaml#
7 title: Xilinx Zynq QSPI controller
10 The Xilinx Zynq QSPI controller is used to access multi-bit serial flash
22 const: xlnx,zynq-qspi-1.0
52 compatible = "xlnx,zynq-qspi-1.0";
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| D | atmel,quadspi.yaml | 7 title: Atmel Quad Serial Peripheral Interface (QSPI)
18 - atmel,sama5d2-qspi
19 - microchip,sam9x60-qspi
20 - microchip,sama7g5-qspi
81 compatible = "atmel,sama5d2-qspi";
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| D | spi-zynqmp-qspi.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
17 const: xlnx,zynqmp-qspi-1.0
49 qspi: spi@ff0f0000 {
50 compatible = "xlnx,zynqmp-qspi-1.0";
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| /Linux-v6.1/arch/m68k/include/asm/ |
| D | mcfqspi.h | 3 * Definitions for Freescale Coldfire QSPI module
12 * struct mcfqspi_cs_control - chip select control for the coldfire qspi driver
18 * The QSPI module has 4 hardware chip selects. We don't use them. Instead
20 * platform data for each QSPI master controller. Only the select and
31 * struct mcfqspi_platform_data - platform data for the coldfire qspi driver
32 * @bus_num: board specific identifier for this qspi driver.
33 * @num_chipselects: number of chip selects supported by this qspi driver.
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | dra7-evm-common.dtsi | 134 &qspi {
153 label = "QSPI.SPL";
157 label = "QSPI.SPL.backup1";
161 label = "QSPI.SPL.backup2";
165 label = "QSPI.SPL.backup3";
169 label = "QSPI.u-boot";
173 label = "QSPI.u-boot-spl-os";
177 label = "QSPI.u-boot-env";
181 label = "QSPI.u-boot-env.backup1";
185 label = "QSPI.kernel";
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| D | r8a7742-iwg21m.dtsi | 39 /* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
40 qspi-en-hog {
84 qspi_pins: qspi {
86 function = "qspi";
90 &qspi {
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| D | socfpga_arria10_socdk_qspi.dts | 9 &qspi {
28 partition@qspi-boot {
33 partition@qspi-rootfs {
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| D | dra72-evm-common.dtsi | 473 &qspi {
492 label = "QSPI.SPL";
496 label = "QSPI.SPL.backup1";
500 label = "QSPI.SPL.backup2";
504 label = "QSPI.SPL.backup3";
508 label = "QSPI.u-boot";
512 label = "QSPI.u-boot-spl-os";
516 label = "QSPI.u-boot-env";
520 label = "QSPI.u-boot-env.backup1";
524 label = "QSPI.kernel";
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