Searched +full:px30 +full:- +full:csi +full:- +full:dphy (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Rockchip SoC MIPI RX0 D-PHY10 - Heiko Stuebner <heiko@sntech.de>13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.19 - rockchip,px30-csi-dphy20 - rockchip,rk1808-csi-dphy[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Rockchip MIPI RX Innosilicon DPHY driver17 #include <linux/phy/phy-mipi-dphy.h>60 /* Configure the count time of the THS-SETTLE by protocol. */71 * The higher 16-bit of this register is used for write protection93 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }145 const struct dphy_drv_data *drv_data = priv->drv_data; in write_grf_reg()146 const struct dphy_reg *reg = &drv_data->grf_regs[index]; in write_grf_reg()148 if (reg->offset) in write_grf_reg()149 regmap_write(priv->grf, reg->offset, in write_grf_reg()[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/px30-cru.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/pinctrl/rockchip.h>11 #include <dt-bindings/power/px30-power.h>12 #include <dt-bindings/soc/rockchip,boot-mode.h>13 #include <dt-bindings/thermal/thermal.h>16 compatible = "rockchip,px30";[all …]
