Lines Matching +full:px30 +full:- +full:csi +full:- +full:dphy
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,px30";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
39 #address-cells = <2>;
40 #size-cells = <0>;
44 compatible = "arm,cortex-a35";
46 enable-method = "psci";
48 #cooling-cells = <2>;
49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
50 dynamic-power-coefficient = <90>;
51 operating-points-v2 = <&cpu0_opp_table>;
56 compatible = "arm,cortex-a35";
58 enable-method = "psci";
60 #cooling-cells = <2>;
61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
62 dynamic-power-coefficient = <90>;
63 operating-points-v2 = <&cpu0_opp_table>;
68 compatible = "arm,cortex-a35";
70 enable-method = "psci";
72 #cooling-cells = <2>;
73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
74 dynamic-power-coefficient = <90>;
75 operating-points-v2 = <&cpu0_opp_table>;
80 compatible = "arm,cortex-a35";
82 enable-method = "psci";
84 #cooling-cells = <2>;
85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
86 dynamic-power-coefficient = <90>;
87 operating-points-v2 = <&cpu0_opp_table>;
90 idle-states {
91 entry-method = "psci";
93 CPU_SLEEP: cpu-sleep {
94 compatible = "arm,idle-state";
95 local-timer-stop;
96 arm,psci-suspend-param = <0x0010000>;
97 entry-latency-us = <120>;
98 exit-latency-us = <250>;
99 min-residency-us = <900>;
102 CLUSTER_SLEEP: cluster-sleep {
103 compatible = "arm,idle-state";
104 local-timer-stop;
105 arm,psci-suspend-param = <0x1010000>;
106 entry-latency-us = <400>;
107 exit-latency-us = <500>;
108 min-residency-us = <2000>;
113 cpu0_opp_table: opp-table-0 {
114 compatible = "operating-points-v2";
115 opp-shared;
117 opp-600000000 {
118 opp-hz = /bits/ 64 <600000000>;
119 opp-microvolt = <950000 950000 1350000>;
120 clock-latency-ns = <40000>;
121 opp-suspend;
123 opp-816000000 {
124 opp-hz = /bits/ 64 <816000000>;
125 opp-microvolt = <1050000 1050000 1350000>;
126 clock-latency-ns = <40000>;
128 opp-1008000000 {
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1175000 1175000 1350000>;
131 clock-latency-ns = <40000>;
133 opp-1200000000 {
134 opp-hz = /bits/ 64 <1200000000>;
135 opp-microvolt = <1300000 1300000 1350000>;
136 clock-latency-ns = <40000>;
138 opp-1296000000 {
139 opp-hz = /bits/ 64 <1296000000>;
140 opp-microvolt = <1350000 1350000 1350000>;
141 clock-latency-ns = <40000>;
145 arm-pmu {
146 compatible = "arm,cortex-a35-pmu";
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 gmac_clkin: external-gmac-clock {
161 compatible = "fixed-clock";
162 clock-frequency = <50000000>;
163 clock-output-names = "gmac_clkin";
164 #clock-cells = <0>;
168 compatible = "arm,psci-1.0";
173 compatible = "arm,armv8-timer";
180 thermal_zones: thermal-zones {
181 soc_thermal: soc-thermal {
182 polling-delay-passive = <20>;
183 polling-delay = <1000>;
184 sustainable-power = <750>;
185 thermal-sensors = <&tsadc 0>;
188 threshold: trip-point-0 {
194 target: trip-point-1 {
200 soc_crit: soc-crit {
207 cooling-maps {
210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
222 gpu_thermal: gpu-thermal {
223 polling-delay-passive = <100>; /* milliseconds */
224 polling-delay = <1000>; /* milliseconds */
225 thermal-sensors = <&tsadc 1>;
230 compatible = "fixed-clock";
231 #clock-cells = <0>;
232 clock-frequency = <24000000>;
233 clock-output-names = "xin24m";
236 pmu: power-management@ff000000 {
237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
240 power: power-controller {
241 compatible = "rockchip,px30-power-controller";
242 #power-domain-cells = <1>;
243 #address-cells = <1>;
244 #size-cells = <0>;
247 power-domain@PX30_PD_USB {
253 #power-domain-cells = <0>;
255 power-domain@PX30_PD_SDCARD {
260 #power-domain-cells = <0>;
262 power-domain@PX30_PD_GMAC {
269 #power-domain-cells = <0>;
271 power-domain@PX30_PD_MMC_NAND {
283 #power-domain-cells = <0>;
285 power-domain@PX30_PD_VPU {
291 #power-domain-cells = <0>;
293 power-domain@PX30_PD_VO {
308 #power-domain-cells = <0>;
310 power-domain@PX30_PD_VI {
320 #power-domain-cells = <0>;
322 power-domain@PX30_PD_GPU {
326 #power-domain-cells = <0>;
332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
334 #address-cells = <1>;
335 #size-cells = <1>;
337 pmu_io_domains: io-domains {
338 compatible = "rockchip,px30-pmu-io-voltage-domain";
342 reboot-mode {
343 compatible = "syscon-reboot-mode";
345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
346 mode-fastboot = <BOOT_FASTBOOT>;
347 mode-loader = <BOOT_BL_DOWNLOAD>;
348 mode-normal = <BOOT_NORMAL>;
349 mode-recovery = <BOOT_RECOVERY>;
354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
358 clock-names = "baudclk", "apb_pclk";
360 dma-names = "tx", "rx";
361 reg-shift = <2>;
362 reg-io-width = <4>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
369 compatible = "rockchip,px30-i2s-tdm";
373 clock-names = "mclk_tx", "mclk_rx", "hclk";
375 dma-names = "tx", "rx";
378 reset-names = "tx-m", "rx-m";
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
386 #sound-dai-cells = <0>;
391 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
395 clock-names = "i2s_clk", "i2s_hclk";
397 dma-names = "tx", "rx";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
401 #sound-dai-cells = <0>;
406 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
410 clock-names = "i2s_clk", "i2s_hclk";
412 dma-names = "tx", "rx";
413 pinctrl-names = "default";
414 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
416 #sound-dai-cells = <0>;
420 gic: interrupt-controller@ff131000 {
421 compatible = "arm,gic-400";
422 #interrupt-cells = <3>;
423 #address-cells = <0>;
424 interrupt-controller;
434 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
436 #address-cells = <1>;
437 #size-cells = <1>;
439 io_domains: io-domains {
440 compatible = "rockchip,px30-io-voltage-domain";
445 compatible = "rockchip,px30-lvds";
447 phy-names = "dphy";
453 #address-cells = <1>;
454 #size-cells = <0>;
458 #address-cells = <1>;
459 #size-cells = <0>;
463 remote-endpoint = <&vopb_out_lvds>;
468 remote-endpoint = <&vopl_out_lvds>;
476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
480 clock-names = "baudclk", "apb_pclk";
482 dma-names = "tx", "rx";
483 reg-shift = <2>;
484 reg-io-width = <4>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
495 clock-names = "baudclk", "apb_pclk";
497 dma-names = "tx", "rx";
498 reg-shift = <2>;
499 reg-io-width = <4>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&uart2m0_xfer>;
506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
510 clock-names = "baudclk", "apb_pclk";
512 dma-names = "tx", "rx";
513 reg-shift = <2>;
514 reg-io-width = <4>;
515 pinctrl-names = "default";
516 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
521 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
525 clock-names = "baudclk", "apb_pclk";
527 dma-names = "tx", "rx";
528 reg-shift = <2>;
529 reg-io-width = <4>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
536 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
540 clock-names = "baudclk", "apb_pclk";
542 dma-names = "tx", "rx";
543 reg-shift = <2>;
544 reg-io-width = <4>;
545 pinctrl-names = "default";
546 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
551 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
554 clock-names = "i2c", "pclk";
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c0_xfer>;
558 #address-cells = <1>;
559 #size-cells = <0>;
564 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
567 clock-names = "i2c", "pclk";
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c1_xfer>;
571 #address-cells = <1>;
572 #size-cells = <0>;
577 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
580 clock-names = "i2c", "pclk";
582 pinctrl-names = "default";
583 pinctrl-0 = <&i2c2_xfer>;
584 #address-cells = <1>;
585 #size-cells = <0>;
590 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
593 clock-names = "i2c", "pclk";
595 pinctrl-names = "default";
596 pinctrl-0 = <&i2c3_xfer>;
597 #address-cells = <1>;
598 #size-cells = <0>;
603 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
607 clock-names = "spiclk", "apb_pclk";
609 dma-names = "tx", "rx";
610 pinctrl-names = "default";
611 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
612 #address-cells = <1>;
613 #size-cells = <0>;
618 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
622 clock-names = "spiclk", "apb_pclk";
624 dma-names = "tx", "rx";
625 pinctrl-names = "default";
626 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
627 #address-cells = <1>;
628 #size-cells = <0>;
633 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
644 clock-names = "pwm", "pclk";
645 pinctrl-names = "default";
646 pinctrl-0 = <&pwm0_pin>;
647 #pwm-cells = <3>;
652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
655 clock-names = "pwm", "pclk";
656 pinctrl-names = "default";
657 pinctrl-0 = <&pwm1_pin>;
658 #pwm-cells = <3>;
663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
666 clock-names = "pwm", "pclk";
667 pinctrl-names = "default";
668 pinctrl-0 = <&pwm2_pin>;
669 #pwm-cells = <3>;
674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
677 clock-names = "pwm", "pclk";
678 pinctrl-names = "default";
679 pinctrl-0 = <&pwm3_pin>;
680 #pwm-cells = <3>;
685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
688 clock-names = "pwm", "pclk";
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm4_pin>;
691 #pwm-cells = <3>;
696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
699 clock-names = "pwm", "pclk";
700 pinctrl-names = "default";
701 pinctrl-0 = <&pwm5_pin>;
702 #pwm-cells = <3>;
707 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
710 clock-names = "pwm", "pclk";
711 pinctrl-names = "default";
712 pinctrl-0 = <&pwm6_pin>;
713 #pwm-cells = <3>;
718 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
721 clock-names = "pwm", "pclk";
722 pinctrl-names = "default";
723 pinctrl-0 = <&pwm7_pin>;
724 #pwm-cells = <3>;
729 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
733 clock-names = "pclk", "timer";
736 dmac: dma-controller@ff240000 {
741 arm,pl330-periph-burst;
743 clock-names = "apb_pclk";
744 #dma-cells = <1>;
748 compatible = "rockchip,px30-tsadc";
751 assigned-clocks = <&cru SCLK_TSADC>;
752 assigned-clock-rates = <50000>;
754 clock-names = "tsadc", "apb_pclk";
756 reset-names = "tsadc-apb";
758 rockchip,hw-tshut-temp = <120000>;
759 pinctrl-names = "init", "default", "sleep";
760 pinctrl-0 = <&tsadc_otp_pin>;
761 pinctrl-1 = <&tsadc_otp_out>;
762 pinctrl-2 = <&tsadc_otp_pin>;
763 #thermal-sensor-cells = <1>;
768 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
771 #io-channel-cells = <1>;
773 clock-names = "saradc", "apb_pclk";
775 reset-names = "saradc-apb";
780 compatible = "rockchip,px30-otp";
784 clock-names = "otp", "apb_pclk", "phy";
786 reset-names = "phy";
787 #address-cells = <1>;
788 #size-cells = <1>;
794 cpu_leakage: cpu-leakage@17 {
803 cru: clock-controller@ff2b0000 {
804 compatible = "rockchip,px30-cru";
807 clock-names = "xin24m", "gpll";
809 #clock-cells = <1>;
810 #reset-cells = <1>;
812 assigned-clocks = <&cru PLL_NPLL>,
817 assigned-clock-rates = <1188000000>,
823 pmucru: clock-controller@ff2bc000 {
824 compatible = "rockchip,px30-pmucru";
827 clock-names = "xin24m";
829 #clock-cells = <1>;
830 #reset-cells = <1>;
832 assigned-clocks =
835 assigned-clock-rates =
841 compatible = "rockchip,px30-usb2phy-grf", "syscon",
842 "simple-mfd";
844 #address-cells = <1>;
845 #size-cells = <1>;
848 compatible = "rockchip,px30-usb2phy";
851 clock-names = "phyclk";
852 #clock-cells = <0>;
853 assigned-clocks = <&cru USB480M>;
854 assigned-clock-parents = <&u2phy>;
855 clock-output-names = "usb480m_phy";
858 u2phy_host: host-port {
859 #phy-cells = <0>;
861 interrupt-names = "linestate";
865 u2phy_otg: otg-port {
866 #phy-cells = <0>;
870 interrupt-names = "otg-bvalid", "otg-id",
878 compatible = "rockchip,px30-dsi-dphy";
881 clock-names = "ref", "pclk";
883 reset-names = "apb";
884 #phy-cells = <0>;
885 power-domains = <&power PX30_PD_VO>;
890 compatible = "rockchip,px30-csi-dphy";
893 clock-names = "pclk";
894 #phy-cells = <0>;
895 power-domains = <&power PX30_PD_VI>;
897 reset-names = "apb";
903 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
908 clock-names = "otg";
910 g-np-tx-fifo-size = <16>;
911 g-rx-fifo-size = <280>;
912 g-tx-fifo-size = <256 128 128 64 32 16>;
914 phy-names = "usb2-phy";
915 power-domains = <&power PX30_PD_USB>;
920 compatible = "generic-ehci";
925 phy-names = "usb";
926 power-domains = <&power PX30_PD_USB>;
931 compatible = "generic-ohci";
936 phy-names = "usb";
937 power-domains = <&power PX30_PD_USB>;
942 compatible = "rockchip,px30-gmac";
945 interrupt-names = "macirq";
950 clock-names = "stmmaceth", "mac_clk_rx",
955 phy-mode = "rmii";
956 pinctrl-names = "default";
957 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
958 power-domains = <&power PX30_PD_GMAC>;
960 reset-names = "stmmaceth";
965 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
970 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
971 bus-width = <4>;
972 fifo-depth = <0x100>;
973 max-frequency = <150000000>;
974 pinctrl-names = "default";
975 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
976 power-domains = <&power PX30_PD_SDCARD>;
981 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
986 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
987 bus-width = <4>;
988 fifo-depth = <0x100>;
989 max-frequency = <150000000>;
990 pinctrl-names = "default";
991 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
992 power-domains = <&power PX30_PD_MMC_NAND>;
997 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1002 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1003 bus-width = <8>;
1004 fifo-depth = <0x100>;
1005 max-frequency = <150000000>;
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1008 power-domains = <&power PX30_PD_MMC_NAND>;
1017 clock-names = "clk_sfc", "hclk_sfc";
1018 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1019 pinctrl-names = "default";
1020 power-domains = <&power PX30_PD_MMC_NAND>;
1024 nfc: nand-controller@ff3b0000 {
1025 compatible = "rockchip,px30-nfc";
1029 clock-names = "ahb", "nfc";
1030 assigned-clocks = <&cru SCLK_NANDC>;
1031 assigned-clock-rates = <150000000>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1035 power-domains = <&power PX30_PD_MMC_NAND>;
1039 gpu_opp_table: opp-table-1 {
1040 compatible = "operating-points-v2";
1042 opp-200000000 {
1043 opp-hz = /bits/ 64 <200000000>;
1044 opp-microvolt = <950000>;
1046 opp-300000000 {
1047 opp-hz = /bits/ 64 <300000000>;
1048 opp-microvolt = <975000>;
1050 opp-400000000 {
1051 opp-hz = /bits/ 64 <400000000>;
1052 opp-microvolt = <1050000>;
1054 opp-480000000 {
1055 opp-hz = /bits/ 64 <480000000>;
1056 opp-microvolt = <1125000>;
1061 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1066 interrupt-names = "job", "mmu", "gpu";
1068 #cooling-cells = <2>;
1069 power-domains = <&power PX30_PD_GPU>;
1070 operating-points-v2 = <&gpu_opp_table>;
1074 vpu: video-codec@ff442000 {
1075 compatible = "rockchip,px30-vpu";
1079 interrupt-names = "vepu", "vdpu";
1081 clock-names = "aclk", "hclk";
1083 power-domains = <&power PX30_PD_VPU>;
1091 clock-names = "aclk", "iface";
1092 #iommu-cells = <0>;
1093 power-domains = <&power PX30_PD_VPU>;
1097 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1101 clock-names = "pclk";
1103 phy-names = "dphy";
1104 power-domains = <&power PX30_PD_VO>;
1106 reset-names = "apb";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1113 #address-cells = <1>;
1114 #size-cells = <0>;
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1123 remote-endpoint = <&vopb_out_dsi>;
1128 remote-endpoint = <&vopl_out_dsi>;
1135 compatible = "rockchip,px30-vop-big";
1140 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1142 reset-names = "axi", "ahb", "dclk";
1144 power-domains = <&power PX30_PD_VO>;
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1153 remote-endpoint = <&dsi_in_vopb>;
1158 remote-endpoint = <&lvds_vopb_in>;
1168 clock-names = "aclk", "iface";
1169 power-domains = <&power PX30_PD_VO>;
1170 #iommu-cells = <0>;
1175 compatible = "rockchip,px30-vop-lit";
1180 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1182 reset-names = "axi", "ahb", "dclk";
1184 power-domains = <&power PX30_PD_VO>;
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1193 remote-endpoint = <&dsi_in_vopl>;
1198 remote-endpoint = <&lvds_vopl_in>;
1208 clock-names = "aclk", "iface";
1209 power-domains = <&power PX30_PD_VO>;
1210 #iommu-cells = <0>;
1215 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1220 interrupt-names = "isp", "mi", "mipi";
1225 clock-names = "isp", "aclk", "hclk", "pclk";
1228 phy-names = "dphy";
1229 power-domains = <&power PX30_PD_VI>;
1233 #address-cells = <1>;
1234 #size-cells = <0>;
1238 #address-cells = <1>;
1239 #size-cells = <0>;
1249 clock-names = "aclk", "iface";
1250 power-domains = <&power PX30_PD_VI>;
1251 rockchip,disable-mmu-reset;
1252 #iommu-cells = <0>;
1256 compatible = "rockchip,px30-qos", "syscon";
1261 compatible = "rockchip,px30-qos", "syscon";
1266 compatible = "rockchip,px30-qos", "syscon";
1271 compatible = "rockchip,px30-qos", "syscon";
1276 compatible = "rockchip,px30-qos", "syscon";
1281 compatible = "rockchip,px30-qos", "syscon";
1286 compatible = "rockchip,px30-qos", "syscon";
1291 compatible = "rockchip,px30-qos", "syscon";
1296 compatible = "rockchip,px30-qos", "syscon";
1301 compatible = "rockchip,px30-qos", "syscon";
1306 compatible = "rockchip,px30-qos", "syscon";
1311 compatible = "rockchip,px30-qos", "syscon";
1316 compatible = "rockchip,px30-qos", "syscon";
1321 compatible = "rockchip,px30-qos", "syscon";
1326 compatible = "rockchip,px30-qos", "syscon";
1331 compatible = "rockchip,px30-qos", "syscon";
1336 compatible = "rockchip,px30-qos", "syscon";
1341 compatible = "rockchip,px30-qos", "syscon";
1346 compatible = "rockchip,px30-qos", "syscon";
1351 compatible = "rockchip,px30-qos", "syscon";
1356 compatible = "rockchip,px30-pinctrl";
1359 #address-cells = <2>;
1360 #size-cells = <2>;
1364 compatible = "rockchip,gpio-bank";
1368 gpio-controller;
1369 #gpio-cells = <2>;
1371 interrupt-controller;
1372 #interrupt-cells = <2>;
1376 compatible = "rockchip,gpio-bank";
1380 gpio-controller;
1381 #gpio-cells = <2>;
1383 interrupt-controller;
1384 #interrupt-cells = <2>;
1388 compatible = "rockchip,gpio-bank";
1392 gpio-controller;
1393 #gpio-cells = <2>;
1395 interrupt-controller;
1396 #interrupt-cells = <2>;
1400 compatible = "rockchip,gpio-bank";
1404 gpio-controller;
1405 #gpio-cells = <2>;
1407 interrupt-controller;
1408 #interrupt-cells = <2>;
1411 pcfg_pull_up: pcfg-pull-up {
1412 bias-pull-up;
1415 pcfg_pull_down: pcfg-pull-down {
1416 bias-pull-down;
1419 pcfg_pull_none: pcfg-pull-none {
1420 bias-disable;
1423 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1424 bias-disable;
1425 drive-strength = <2>;
1428 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1429 bias-pull-up;
1430 drive-strength = <2>;
1433 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1434 bias-pull-up;
1435 drive-strength = <4>;
1438 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1439 bias-disable;
1440 drive-strength = <4>;
1443 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1444 bias-pull-down;
1445 drive-strength = <4>;
1448 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1449 bias-disable;
1450 drive-strength = <8>;
1453 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1454 bias-pull-up;
1455 drive-strength = <8>;
1458 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1459 bias-disable;
1460 drive-strength = <12>;
1463 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1464 bias-pull-up;
1465 drive-strength = <12>;
1468 pcfg_pull_none_smt: pcfg-pull-none-smt {
1469 bias-disable;
1470 input-schmitt-enable;
1473 pcfg_output_high: pcfg-output-high {
1474 output-high;
1477 pcfg_output_low: pcfg-output-low {
1478 output-low;
1481 pcfg_input_high: pcfg-input-high {
1482 bias-pull-up;
1483 input-enable;
1486 pcfg_input: pcfg-input {
1487 input-enable;
1491 i2c0_xfer: i2c0-xfer {
1499 i2c1_xfer: i2c1-xfer {
1507 i2c2_xfer: i2c2-xfer {
1515 i2c3_xfer: i2c3-xfer {
1523 tsadc_otp_pin: tsadc-otp-pin {
1528 tsadc_otp_out: tsadc-otp-out {
1535 uart0_xfer: uart0-xfer {
1541 uart0_cts: uart0-cts {
1546 uart0_rts: uart0-rts {
1553 uart1_xfer: uart1-xfer {
1559 uart1_cts: uart1-cts {
1564 uart1_rts: uart1-rts {
1570 uart2-m0 {
1571 uart2m0_xfer: uart2m0-xfer {
1578 uart2-m1 {
1579 uart2m1_xfer: uart2m1-xfer {
1586 uart3-m0 {
1587 uart3m0_xfer: uart3m0-xfer {
1593 uart3m0_cts: uart3m0-cts {
1598 uart3m0_rts: uart3m0-rts {
1604 uart3-m1 {
1605 uart3m1_xfer: uart3m1-xfer {
1611 uart3m1_cts: uart3m1-cts {
1616 uart3m1_rts: uart3m1-rts {
1623 uart4_xfer: uart4-xfer {
1629 uart4_cts: uart4-cts {
1634 uart4_rts: uart4-rts {
1641 uart5_xfer: uart5-xfer {
1647 uart5_cts: uart5-cts {
1652 uart5_rts: uart5-rts {
1659 spi0_clk: spi0-clk {
1664 spi0_csn: spi0-csn {
1669 spi0_miso: spi0-miso {
1674 spi0_mosi: spi0-mosi {
1679 spi0_clk_hs: spi0-clk-hs {
1684 spi0_miso_hs: spi0-miso-hs {
1689 spi0_mosi_hs: spi0-mosi-hs {
1696 spi1_clk: spi1-clk {
1701 spi1_csn0: spi1-csn0 {
1706 spi1_csn1: spi1-csn1 {
1711 spi1_miso: spi1-miso {
1716 spi1_mosi: spi1-mosi {
1721 spi1_clk_hs: spi1-clk-hs {
1726 spi1_miso_hs: spi1-miso-hs {
1731 spi1_mosi_hs: spi1-mosi-hs {
1738 pdm_clk0m0: pdm-clk0m0 {
1743 pdm_clk0m1: pdm-clk0m1 {
1748 pdm_clk1: pdm-clk1 {
1753 pdm_sdi0m0: pdm-sdi0m0 {
1758 pdm_sdi0m1: pdm-sdi0m1 {
1763 pdm_sdi1: pdm-sdi1 {
1768 pdm_sdi2: pdm-sdi2 {
1773 pdm_sdi3: pdm-sdi3 {
1778 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1783 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1788 pdm_clk1_sleep: pdm-clk1-sleep {
1793 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1798 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1803 pdm_sdi1_sleep: pdm-sdi1-sleep {
1808 pdm_sdi2_sleep: pdm-sdi2-sleep {
1813 pdm_sdi3_sleep: pdm-sdi3-sleep {
1820 i2s0_8ch_mclk: i2s0-8ch-mclk {
1825 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1830 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1835 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1840 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1845 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1850 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1855 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1860 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1865 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1870 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1875 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1880 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1887 i2s1_2ch_mclk: i2s1-2ch-mclk {
1892 i2s1_2ch_sclk: i2s1-2ch-sclk {
1897 i2s1_2ch_lrck: i2s1-2ch-lrck {
1902 i2s1_2ch_sdi: i2s1-2ch-sdi {
1907 i2s1_2ch_sdo: i2s1-2ch-sdo {
1914 i2s2_2ch_mclk: i2s2-2ch-mclk {
1919 i2s2_2ch_sclk: i2s2-2ch-sclk {
1924 i2s2_2ch_lrck: i2s2-2ch-lrck {
1929 i2s2_2ch_sdi: i2s2-2ch-sdi {
1934 i2s2_2ch_sdo: i2s2-2ch-sdo {
1941 sdmmc_clk: sdmmc-clk {
1946 sdmmc_cmd: sdmmc-cmd {
1951 sdmmc_det: sdmmc-det {
1956 sdmmc_bus1: sdmmc-bus1 {
1961 sdmmc_bus4: sdmmc-bus4 {
1971 sdio_clk: sdio-clk {
1976 sdio_cmd: sdio-cmd {
1981 sdio_bus4: sdio-bus4 {
1991 emmc_clk: emmc-clk {
1996 emmc_cmd: emmc-cmd {
2001 emmc_rstnout: emmc-rstnout {
2006 emmc_bus1: emmc-bus1 {
2011 emmc_bus4: emmc-bus4 {
2019 emmc_bus8: emmc-bus8 {
2033 flash_cs0: flash-cs0 {
2038 flash_rdy: flash-rdy {
2043 flash_dqs: flash-dqs {
2048 flash_ale: flash-ale {
2053 flash_cle: flash-cle {
2058 flash_wrn: flash-wrn {
2063 flash_csl: flash-csl {
2068 flash_rdn: flash-rdn {
2073 flash_bus8: flash-bus8 {
2087 sfc_bus4: sfc-bus4 {
2095 sfc_bus2: sfc-bus2 {
2101 sfc_cs0: sfc-cs0 {
2106 sfc_clk: sfc-clk {
2113 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2118 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2123 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2128 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2133 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2161 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2183 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2203 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2224 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2239 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2254 pwm0_pin: pwm0-pin {
2261 pwm1_pin: pwm1-pin {
2268 pwm2_pin: pwm2-pin {
2275 pwm3_pin: pwm3-pin {
2282 pwm4_pin: pwm4-pin {
2289 pwm5_pin: pwm5-pin {
2296 pwm6_pin: pwm6-pin {
2303 pwm7_pin: pwm7-pin {
2310 rmii_pins: rmii-pins {
2323 mac_refclk_12ma: mac-refclk-12ma {
2328 mac_refclk: mac-refclk {
2334 cif-m0 {
2335 cif_clkout_m0: cif-clkout-m0 {
2340 dvp_d2d9_m0: dvp-d2d9-m0 {
2356 dvp_d0d1_m0: dvp-d0d1-m0 {
2362 dvp_d10d11_m0:d10-d11-m0 {
2369 cif-m1 {
2370 cif_clkout_m1: cif-clkout-m1 {
2375 dvp_d2d9_m1: dvp-d2d9-m1 {
2391 dvp_d0d1_m1: dvp-d0d1-m1 {
2397 dvp_d10d11_m1:d10-d11-m1 {
2405 isp_prelight: isp-prelight {