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/Linux-v6.1/drivers/phy/cadence/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Cadence PHYs
7 tristate "Cadence Torrent PHY driver"
13 Support for Cadence Torrent PHY.
16 tristate "Cadence D-PHY Support"
21 Choose this option if you have a Cadence D-PHY in your
23 cdns-dphy.
26 tristate "Cadence D-PHY Rx Support"
31 Support for Cadence D-PHY in Rx configuration.
34 tristate "Cadence Sierra PHY Driver"
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DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_PHY_CADENCE_TORRENT) += phy-cadence-torrent.o
3 obj-$(CONFIG_PHY_CADENCE_DPHY) += cdns-dphy.o
4 obj-$(CONFIG_PHY_CADENCE_DPHY_RX) += cdns-dphy-rx.o
5 obj-$(CONFIG_PHY_CADENCE_SIERRA) += phy-cadence-sierra.o
6 obj-$(CONFIG_PHY_CADENCE_SALVO) += phy-cadence-salvo.o
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Torrent SD0801 PHY binding
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
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Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Sierra PHY binding
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
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Dcdns,salvo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Cadence SALVO PHY
11 - Peter Chen <peter.chen@nxp.com>
16 - nxp,salvo-phy
24 clock-names:
26 - const: salvo_phy_clk
28 power-domains:
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Dcdns,dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/cdns,dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence DPHY Rx
10 - Pratyush Yadav <pratyush@kernel.org>
15 - const: cdns,dphy-rx
20 "#phy-cells":
23 power-domains:
27 - compatible
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Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,am64-wiz-10g
19 - ti,j7200-wiz-10g
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/Linux-v6.1/drivers/ufs/host/
DKconfig1 # SPDX-License-Identifier: GPL-2.0+
5 # Copyright (C) 2011-2013 Samsung India Software Operations
26 Synopsys Test Chip is a PHY for prototyping purposes.
42 tristate "Cadence UFS Controller platform driver"
45 This selects the Cadence-specific additions to UFSHCD platform driver.
53 Synopsys Test Chip is a PHY for prototyping purposes.
65 accessing the hardware which includes PHY configuration and vendor
79 accessing the hardware which includes PHY configuration and vendor
108 tristate "TI glue layer for Cadence UFS Controller"
111 This selects driver for TI glue layer for Cadence UFS Host
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/Linux-v6.1/drivers/usb/cdns3/
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Cadence USBSS and USBSSP DRD Header File.
5 * Copyright (C) 2017-2018 NXP
6 * Copyright (C) 2018-2019 Cadence.
9 * Pawel Laszczak <pawell@cadence.com>
20 * struct cdns_role_driver - host/gadget role driver
50 * struct cdns - Representation of Cadence USB3 DRD controller.
51 * @dev: pointer to Cadence device struct
68 * @usb2_phy: pointer to USB2 PHY
69 * @usb3_phy: pointer to USB3 PHY
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Dcdns3-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence USBSS DRD Driver.
5 * Copyright (C) 2018-2020 Cadence.
6 * Copyright (C) 2017-2018 NXP
11 * Pawel Laszczak <pawell@cadence.com>
22 #include "gadget-export.h"
29 ret = phy_power_on(cdns->usb2_phy); in set_phy_power_on()
33 ret = phy_power_on(cdns->usb3_phy); in set_phy_power_on()
35 phy_power_off(cdns->usb2_phy); in set_phy_power_on()
42 phy_power_off(cdns->usb3_phy); in set_phy_power_off()
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/Linux-v6.1/Documentation/devicetree/bindings/display/bridge/
Dcdns,mhdp8546.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
16 - cdns,mhdp8546
17 - ti,j721e-mhdp8546
22 - description:
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
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Dcdns,dsi.txt1 Cadence DSI bridge
4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dcdns-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence PCIe Core
10 - Tom Joseph <tjoseph@cadence.com>
15 One per lane if more than one in the list. If only one PHY listed it must
20 phy-names:
22 - const: pcie-phy
Dcdns,cdns-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe EP Controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: "cdns-pcie-ep.yaml#"
17 const: cdns,cdns-pcie-ep
22 reg-names:
24 - const: reg
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Dcdns,cdns-pcie-host.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence PCIe host controller
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: "cdns-pcie-host.yaml#"
18 const: cdns,cdns-pcie-host
23 reg-names:
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/Linux-v6.1/drivers/pci/controller/cadence/
Dpcie-cadence-plat.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cadence PCIe platform driver.
5 * Copyright (c) 2019, Cadence Design Systems
6 * Author: Tom Joseph <tjoseph@cadence.com>
14 #include "pcie-cadence.h"
19 * struct cdns_plat_pcie - private data for this PCIe platform driver
20 * @pcie: Cadence PCIe controller
48 struct device *dev = &pdev->dev; in cdns_plat_pcie_probe()
58 return -EINVAL; in cdns_plat_pcie_probe()
60 is_rc = data->is_rc; in cdns_plat_pcie_probe()
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Dpcie-cadence.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
8 #include "pcie-cadence.h"
34 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
75 if (pcie->is_rc) { in cdns_pcie_set_outbound_region()
92 if (pcie->ops->cpu_addr_fixup) in cdns_pcie_set_outbound_region()
93 cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr); in cdns_pcie_set_outbound_region()
113 if (pcie->is_rc) { in cdns_pcie_set_outbound_region_for_normal_msg()
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Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
12 #include <linux/phy/phy.h>
117 (((aperture) - 2) << ((bar) * 8))
149 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
189 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
200 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
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/Linux-v6.1/Documentation/devicetree/bindings/usb/
Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
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/Linux-v6.1/Documentation/devicetree/bindings/media/
Dcdns,csi2rx.txt1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
[all …]
Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
[all …]
/Linux-v6.1/drivers/spi/
Dspi-cadence-xspi.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Cadence XSPI flash controller driver
3 // Copyright (C) 2020-21 Cadence
19 #include <linux/spi/spi-mem.h>
26 #define CDNS_XSPI_NAME "cadence-xspi"
30 * configure XSPI controller pin-strap settings
33 /* PHY DQ timing register */
36 /* PHY DQS timing register */
39 /* PHY gate loopback control register */
42 /* PHY DLL slave control register */
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/Linux-v6.1/drivers/phy/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_GENERIC_PHY) += phy-core.o
7 obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
8 obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
9 obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
10 obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
11 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
12 obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
13 obj-y += allwinner/ \
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/Linux-v6.1/drivers/mmc/host/
Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include "sdhci-pltfm.h"
18 /* HRS - Host Register Set (specific to Cadence) */
19 #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
38 /* SRS - Slot Register Set (SDHCI-compatible) */
41 /* PHY */
56 * The tuned val register is 6 bit-wide, but not the whole of the range is
57 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
80 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
81 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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/Linux-v6.1/Documentation/devicetree/bindings/ufs/
Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
24 - $ref: ufs-common.yaml
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