Lines Matching +full:phy +full:- +full:cadence
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence Sierra PHY binding
10 This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
29 '#clock-cells':
35 - description: Sierra PHY reset.
36 - description: Sierra APB reset. This is optional.
38 reset-names:
41 - const: sierra_reset
42 - const: sierra_apb
47 Offset of the Sierra PHY configuration registers.
49 reg-names:
56 clock-names:
59 - const: cmn_refclk_dig_div
60 - const: cmn_refclk1_dig_div
61 - const: pll0_refclk
62 - const: pll1_refclk
64 assigned-clocks:
68 assigned-clock-parents:
75 A boolean property whose presence indicates that the PHY registers will be
76 configured by hardware. If not present, all sub-node optional properties
80 '^phy@[0-9a-f]$':
83 Each group of PHY lanes with a single master lane should be represented as
84 a sub-node. Note that the actual configuration of each lane is determined
99 "#phy-cells":
102 cdns,phy-type:
104 Specifies the type of PHY for which the group of PHY lanes is used.
105 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
109 cdns,num-lanes:
116 cdns,ssc-mode:
120 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
126 - reg
127 - resets
128 - "#phy-cells"
133 - compatible
134 - "#address-cells"
135 - "#size-cells"
136 - reg
137 - resets
138 - reset-names
143 - |
144 #include <dt-bindings/phy/phy.h>
147 #address-cells = <2>;
148 #size-cells = <2>;
150 sierra-phy@fd240000 {
151 compatible = "cdns,sierra-phy-t0";
154 reset-names = "sierra_reset", "sierra_apb";
156 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 pcie0_phy0: phy@0 {
162 cdns,num-lanes = <2>;
163 #phy-cells = <0>;
164 cdns,phy-type = <PHY_TYPE_PCIE>;
166 pcie0_phy1: phy@2 {
169 cdns,num-lanes = <1>;
170 #phy-cells = <0>;
171 cdns,phy-type = <PHY_TYPE_PCIE>;