| /Linux-v6.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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| D | fsl-ls1088a-ten64.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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| D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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| /Linux-v6.1/Documentation/devicetree/bindings/net/ |
| D | nvidia,tegra234-mgbe.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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| D | xilinx_axienet.txt | 2 --------------------------------------------------------
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
22 axistream-connected is specified, in which case the reg
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25 and optionally Ethernet core. If axistream-connected is
29 - phy-handle : Should point to the external phy device if exists. Pointing
30 this to the PCS/PMA PHY is deprecated and should be avoided.
32 - xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware
[all …]
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| D | fsl,qoriq-mc-dpmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: "ethernet-controller.yaml#"
21 const: fsl,qoriq-mc-dpmac
27 phy-handle: true
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| D | fsl,fman-dtsec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman-dtsec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Madalin Bucur <madalin.bucur@nxp.com>
15 10/100/1000 MBit/s speeds, and the 10-Gigabit Ethernet Media Access Controller
17 Ethernet Media Access Controller (mEMAC) to handle all speeds.
22 - fsl,fman-dtsec
23 - fsl,fman-xgec
24 - fsl,fman-memac
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| D | fsl-fman.txt | 5 - FMan Node
6 - FMan Port Node
7 - FMan MURAM Node
8 - FMan dTSEC/XGEC/mEMAC Node
9 - FMan IEEE 1588 Node
10 - FMan MDIO Node
11 - Example
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
23 - compatible
32 - cell-index
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| D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
20 local-mac-address:
23 $ref: /schemas/types.yaml#/definitions/uint8-array
27 mac-address:
32 local-mac-address property.
33 $ref: /schemas/types.yaml#/definitions/uint8-array
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| D | altr,tse.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Chevallier <maxime.chevallier@bootlin.com>
15 - const: altr,tse-1.0
16 - const: ALTR,tse-1.0
18 - const: altr,tse-msgdma-1.0
23 interrupt-names:
25 - const: rx_irq
26 - const: tx_irq
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| /Linux-v6.1/Documentation/devicetree/bindings/net/dsa/ |
| D | renesas,rzn1-a5psw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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| /Linux-v6.1/drivers/net/ethernet/freescale/dpaa2/ |
| D | dpaa2-mac.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 #include <linux/pcs-lynx.h>
9 #include "dpaa2-eth.h"
10 #include "dpaa2-mac.h"
23 if (mac->ver_major == ver_major) in dpaa2_mac_cmp_ver()
24 return mac->ver_minor - ver_minor; in dpaa2_mac_cmp_ver()
25 return mac->ver_major - ver_major; in dpaa2_mac_cmp_ver()
30 mac->features = 0; in dpaa2_mac_detect_features()
34 mac->features |= DPAA2_MAC_FEATURE_PROTOCOL_CHANGE; in dpaa2_mac_detect_features()
58 return -EINVAL; in phy_mode()
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| /Linux-v6.1/drivers/pinctrl/ |
| D | pinctrl-single.c | 29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
117 * struct pcs_data - wrapper for data needed by pinctrl framework
131 * struct pcs_soc_data - SoC specific settings
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| /Linux-v6.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-socfpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
54 struct tse_pcs pcs; member
61 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
62 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
63 struct device *dev = dwmac->dev; in socfpga_dwmac_fix_mac_speed()
65 struct phy_device *phy_dev = ndev->phydev; in socfpga_dwmac_fix_mac_speed()
95 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed); in socfpga_dwmac_fix_mac_speed()
101 struct device_node *np = dev->of_node; in socfpga_dwmac_parse_data()
[all …]
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| /Linux-v6.1/Documentation/devicetree/bindings/phy/ |
| D | ti-phy.txt | 6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
13 set PCS delay value.
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
[all …]
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | ls1021a-tsn.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
[all …]
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| D | r9a06g032.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
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| /Linux-v6.1/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_port.c | 1 // SPDX-License-Identifier: GPL-2.0+
30 status->an_complete = true; in decode_sgmii_word()
32 status->link = false; in decode_sgmii_word()
38 status->speed = SPEED_10; in decode_sgmii_word()
41 status->speed = SPEED_100; in decode_sgmii_word()
44 status->speed = SPEED_1000; in decode_sgmii_word()
47 status->link = false; in decode_sgmii_word()
51 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
53 status->duplex = DUPLEX_HALF; in decode_sgmii_word()
58 status->link = !(lp_abil & ADVERTISE_RFAULT) && status->link; in decode_cl37_word()
[all …]
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| /Linux-v6.1/drivers/net/phy/ |
| D | phylink.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * technologies such as SFP cages where the PHY is hot-pluggable.
40 * struct phylink - internal data type for phylink
47 struct phylink_pcs *pcs; member
56 u8 link_port; /* The current non-phy ethtool port */
87 if ((pl)->config->type == PHYLINK_NETDEV) \
88 netdev_printk(level, (pl)->netdev, fmt, ##__VA_ARGS__); \
89 else if ((pl)->config->type == PHYLINK_DEV) \
90 dev_printk(level, (pl)->dev, fmt, ##__VA_ARGS__); \
102 if ((pl)->config->type == PHYLINK_NETDEV) \
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| /Linux-v6.1/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | mac-phy-support.rst | 1 .. SPDX-License-Identifier: GPL-2.0
11 --------
14 drivers (dpaa2-eth, dpaa2-ethsw) interract with the PHY library.
17 ---------------------------
19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
20 network interface) and DPMAC objects (abstracting a MAC). The dpaa2-eth driver
26 directly by the dpaa2-eth driver or by phylink.
28 .. code-block:: none
32 +--------------------------------------+
33 +------------+ +---------+ | xgmac_mdio |
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| /Linux-v6.1/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
7 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
9 * Copyright (c) 2010 - 2011 PetaLogix
10 * Copyright (c) 2019 - 2022 Calian Advanced Technologies
11 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
17 * - Add Axi Fifo support.
18 * - Factor out Axi DMA code into separate driver.
19 * - Test and fix basic multicast filtering.
[all …]
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| /Linux-v6.1/fs/erofs/ |
| D | zdata.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 if (iter->bvpage) in z_erofs_bvec_iter_end()
40 kunmap_local(iter->bvset); in z_erofs_bvec_iter_end()
41 return iter->bvpage; in z_erofs_bvec_iter_end()
46 unsigned long base = (unsigned long)((struct z_erofs_bvset *)0)->bvec; in z_erofs_bvset_flip()
48 struct page *nextpage = iter->bvset->nextpage; in z_erofs_bvset_flip()
53 iter->bvpage = nextpage; in z_erofs_bvset_flip()
54 iter->bvset = kmap_local_page(nextpage); in z_erofs_bvset_flip()
55 iter->nr = (PAGE_SIZE - base) / sizeof(struct z_erofs_bvec); in z_erofs_bvset_flip()
56 iter->cur = 0; in z_erofs_bvset_flip()
[all …]
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| /Linux-v6.1/include/linux/ |
| D | kcov.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 * Covered PCs are collected in a per-task buffer.
33 (t)->kcov_mode |= KCOV_IN_CTXSW; \
38 (t)->kcov_mode &= ~KCOV_IN_CTXSW; \
41 /* See Documentation/dev-tools/kcov.rst for usage details. */
42 void kcov_remote_start(u64 handle);
81 static inline void kcov_remote_start(u64 handle) {} in kcov_remote_start() argument
|
| /Linux-v6.1/drivers/phy/qualcomm/ |
| D | phy-qcom-qmp-ufs.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
78 /* set of registers with offsets different per-PHY */
80 /* PCS registers */
534 /* struct qmp_phy_cfg - per-PHY initialization config */
538 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
563 /* true, if PCS block has no separate SW_RESET register */
[all …]
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