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/Linux-v5.15/Documentation/devicetree/bindings/spi/
Domap-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/omap-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Aswath Govindraju <a-govindraju@ti.com>
13 - $ref: spi-controller.yaml#
18 - items:
19 - enum:
20 - ti,am654-mcspi
21 - ti,am4372-mcspi
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/Linux-v5.15/arch/arm64/boot/dts/ti/
Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,am64-uart", "ti,am654-uart";
13 clock-frequency = <48000000>;
14 current-speed = <115200>;
15 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
17 clock-names = "fclk";
21 compatible = "ti,am64-uart", "ti,am654-uart";
24 clock-frequency = <48000000>;
25 current-speed = <115200>;
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Dk3-am65-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
9 mcu_conf: scm-conf@40f00000 {
10 compatible = "syscon", "simple-mfd";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 compatible = "ti,am654-phy-gmii-sel";
19 #phy-cells = <1>;
24 compatible = "ti,am654-uart";
27 clock-frequency = <96000000>;
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Dk3-am64-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/phy/phy-cadence.h>
9 #include <dt-bindings/phy/phy-ti.h>
12 serdes_refclk: clock-cmnrefclk {
13 #clock-cells = <0>;
14 compatible = "fixed-clock";
15 clock-frequency = <0>;
21 compatible = "mmio-sram";
23 #address-cells = <1>;
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Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/Linux-v5.15/arch/arm/boot/dts/
Ddm814x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm814.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/dm814x.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 compatible = "arm,cortex-a8";
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Dam437x-l4.dtsi2 compatible = "ti,am4-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
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Domap4-l4.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 compatible = "ti,omap4-l4-cfg", "simple-pm-bus";
4 power-domains = <&prm_core>;
6 clock-names = "fck";
10 reg-names = "ap", "la", "ia0";
11 #address-cells = <1>;
12 #size-cells = <1>;
22 compatible = "simple-pm-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
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Domap5-l4.dtsi2 compatible = "ti,omap5-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_core>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
21 compatible = "simple-pm-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
55 target-module@2000 { /* 0x4a002000, ap 3 44.0 */
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Ddm816x.dtsi7 #include <dt-bindings/bus/ti-sysc.h>
8 #include <dt-bindings/clock/dm816.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/omap.h>
14 interrupt-parent = <&intc>;
15 #address-cells = <1>;
16 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
33 compatible = "arm,cortex-a8";
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Ddra7-l4.dtsi2 compatible = "ti,dra7-l4-cfg", "simple-pm-bus";
3 power-domains = <&prm_coreaon>;
5 clock-names = "fck";
9 reg-names = "ap", "la", "ia0";
10 #address-cells = <1>;
11 #size-cells = <1>;
17 compatible = "simple-pm-bus";
18 #address-cells = <1>;
19 #size-cells = <1>;
50 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
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Dam33xx-l4.dtsi2 compatible = "ti,am33xx-l4-wkup", "simple-pm-bus";
3 power-domains = <&prm_wkup>;
5 clock-names = "fck";
10 reg-names = "ap", "la", "ia0", "ia1";
11 #address-cells = <1>;
12 #size-cells = <1>;
18 compatible = "simple-pm-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
28 compatible = "simple-pm-bus";
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/Linux-v5.15/drivers/spi/
Dspi-omap2-mcspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * OMAP2 McSPI controller driver
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); in mcspi_write_reg() local
149 writel_relaxed(val, mcspi->base + idx); in mcspi_write_reg()
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master); in mcspi_read_reg() local
156 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
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/Linux-v5.15/arch/arm/mach-omap2/
Domap_hwmod_81xx_data.c4 * Copyright (C) 2010 Texas Instruments, Inc. - https://www.ti.com/
20 #include <linux/platform_data/hsmmc-omap.h>
34 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS"
87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE)
88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE)
89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE)
90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE)
91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE)
92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE)
93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE)
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/Linux-v5.15/drivers/bus/
Dti-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
22 #include <linux/platform_data/ti-sysc.h>
24 #include <dt-bindings/bus/ti-sysc.h>
86 * struct sysc - TI sysc interconnect target module registers and capabilities
92 * @mdata: ti-sysc to hwmod translation data for a module
109 * @pre_reset_quirk: module specific pre-reset quirk
110 * @post_reset_quirk: module specific post-reset quirk
153 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { in sysc_write()
154 writew_relaxed(value & 0xffff, ddata->module_va + offset); in sysc_write()
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