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/Linux-v6.1/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
Dmvebu-pci.txt5 - compatible: one of the following values:
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
10 - #address-cells, set to <3>
11 - #size-cells, set to <2>
12 - #interrupt-cells, set to <1>
13 - bus-range: PCI bus numbers covered
14 - device_type, set to "pci"
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Dsamsung,exynos-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Szyprowski <m.szyprowski@samsung.com>
11 - Jaehoon Chung <jh80.chung@samsung.com>
16 snps,dw-pcie.yaml.
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 const: samsung,exynos5433-pcie
27 - description: Data Bus Interface (DBI) registers.
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Dtoshiba,visconti-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
16 - $ref: /schemas/pci/snps,dw-pcie.yaml#
20 const: toshiba,visconti-pcie
24 - description: Data Bus Interface (DBI) registers.
25 - description: PCIe configuration space region.
26 - description: Visconti specific additional registers.
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Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
17 - $ref: /schemas/pci/pci-bus.yaml#
22 - {}
23 - const: snps,dw-pcie
33 reg-names:
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Dintel,keembay-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
11 - Srikanth Thokala <srikanth.thokala@intel.com>
15 const: intel,keembay-pcie-ep
20 reg-names:
22 - const: dbi
23 - const: dbi2
[all …]
Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
24 - socionext,uniphier-pro5-pcie-ep
25 - socionext,uniphier-nx1-pcie-ep
31 reg-names:
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Drockchip-pcie-ep.txt4 - compatible: Should contain "rockchip,rk3399-pcie-ep"
5 - reg: Two register ranges as listed in the reg-names property
6 - reg-names: Must include the following names
7 - "apb-base"
8 - "mem-base"
9 - clocks: Must contain an entry for each entry in clock-names.
10 See ../clocks/clock-bindings.txt for details.
11 - clock-names: Must include the following entries:
12 - "aclk"
13 - "aclk-perf"
[all …]
Drockchip-dw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
17 designware-pcie.txt.
20 - $ref: /schemas/pci/pci-bus.yaml#
25 - const: rockchip,rk3568-pcie
[all …]
Dsifive,fu740-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Paul Walmsley <paul.walmsley@sifive.com>
17 - Greentime Hu <greentime.hu@sifive.com>
20 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 const: sifive,fu740-pcie
29 reg-names:
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Dintel,keembay-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
11 - Srikanth Thokala <srikanth.thokala@intel.com>
14 - $ref: /schemas/pci/pci-bus.yaml#
18 const: intel,keembay-pcie
23 reset-gpios:
29 reg-names:
[all …]
Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
24 - socionext,uniphier-pcie
30 reg-names:
33 - const: dbi
[all …]
Drockchip-pcie-host.txt4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
14 See ../clocks/clock-bindings.txt for details.
[all …]
Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../snps,dw-pcie.yaml
[all …]
Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
22 - const: ti,am64-pcie-ep
[all …]
Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/phy/
Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
[all …]
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
[all …]
/Linux-v6.1/arch/arm64/boot/dts/marvell/
Dcn9132-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9132-DB board.
8 #include "cn9131-db.dtsi"
12 "marvell,armada-ap807-quad", "marvell,armada-ap807";
21 compatible = "regulator-fixed";
22 regulator-name = "cp2-xhci0-vbus";
23 regulator-min-microvolt = <5000000>;
24 regulator-max-microvolt = <5000000>;
25 enable-active-high;
30 compatible = "usb-nop-xceiv";
[all …]
Dcn9130-crb-B.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-B";
14 num-lanes = <1>;
15 num-viewport = <8>;
16 /* Generic PHY, providing serdes lanes */
18 iommu-map =
22 iommu-map-mask = <0x031f>;
27 sata-port@0 {
29 /* Generic PHY, providing serdes lanes */
[all …]
Dcn9131-db.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Device tree for the CN9131-DB board.
8 #include "cn9130-db.dtsi"
12 "marvell,armada-ap807-quad", "marvell,armada-ap807";
22 compatible = "regulator-fixed";
23 pinctrl-names = "default";
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
25 regulator-name = "cp1-xhci0-vbus";
26 regulator-min-microvolt = <5000000>;
27 regulator-max-microvolt = <5000000>;
[all …]
Dcn9130-crb-A.dts1 // SPDX-License-Identifier: GPL-2.0+
6 #include "cn9130-crb.dtsi"
9 model = "Marvell Armada CN9130-CRB-A";
14 num-lanes = <4>;
15 num-viewport = <8>;
16 /* Generic PHY, providing serdes lanes */
21 iommu-map =
25 iommu-map-mask = <0x031f>;
30 usb-phy = <&cp0_usb3_0_phy0>;
31 phy-names = "usb";
[all …]
/Linux-v6.1/arch/arm64/boot/dts/ti/
Dk3-j721e-common-proc-board.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
15 compatible = "ti,j721e-evm", "ti,j721e";
19 stdout-path = "serial2:115200n8";
[all …]
/Linux-v6.1/drivers/phy/qualcomm/
Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
23 #include <dt-bindings/phy/phy.h>
25 #include "phy-qcom-qmp.h"
46 * if yes, then offset gives index in the reg-layout
50 * mask of lanes for which this register is written
78 /* set of registers with offsets different per-PHY */
534 /* struct qmp_phy_cfg - per-PHY initialization config */
536 int lanes; member
538 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
[all …]
/Linux-v6.1/drivers/pci/controller/
Dpcie-rockchip.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Wenrui Li <wenrui.li@rock-chips.com>
23 #include "pcie-rockchip.h"
27 struct device *dev = rockchip->dev; in rockchip_pcie_parse_dt()
29 struct device_node *node = dev->of_node; in rockchip_pcie_parse_dt()
33 if (rockchip->is_rc) { in rockchip_pcie_parse_dt()
36 "axi-base"); in rockchip_pcie_parse_dt()
37 rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs); in rockchip_pcie_parse_dt()
38 if (IS_ERR(rockchip->reg_base)) in rockchip_pcie_parse_dt()
[all …]

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