Lines Matching +full:num +full:- +full:lanes
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
15 compatible = "ti,j721e-evm", "ti,j721e";
19 stdout-path = "serial2:115200n8";
23 gpio_keys: gpio-keys {
24 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
29 sw10: switch-10 {
35 sw11: switch-11 {
42 evm_12v0: fixedregulator-evm12v0 {
44 compatible = "regulator-fixed";
45 regulator-name = "evm_12v0";
46 regulator-min-microvolt = <12000000>;
47 regulator-max-microvolt = <12000000>;
48 regulator-always-on;
49 regulator-boot-on;
52 vsys_3v3: fixedregulator-vsys3v3 {
54 compatible = "regulator-fixed";
55 regulator-name = "vsys_3v3";
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 vin-supply = <&evm_12v0>;
59 regulator-always-on;
60 regulator-boot-on;
63 vsys_5v0: fixedregulator-vsys5v0 {
65 compatible = "regulator-fixed";
66 regulator-name = "vsys_5v0";
67 regulator-min-microvolt = <5000000>;
68 regulator-max-microvolt = <5000000>;
69 vin-supply = <&evm_12v0>;
70 regulator-always-on;
71 regulator-boot-on;
74 vdd_mmc1: fixedregulator-sd {
75 compatible = "regulator-fixed";
76 regulator-name = "vdd_mmc1";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 regulator-boot-on;
80 enable-active-high;
81 vin-supply = <&vsys_3v3>;
85 vdd_sd_dv_alt: gpio-regulator-TLV71033 {
86 compatible = "regulator-gpio";
87 pinctrl-names = "default";
88 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
89 regulator-name = "tlv71033";
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <3300000>;
92 regulator-boot-on;
93 vin-supply = <&vsys_5v0>;
100 compatible = "ti,j721e-cpb-audio";
101 model = "j721e-cpb";
103 ti,cpb-mcasp = <&mcasp10>;
104 ti,cpb-codec = <&pcm3168a_1>;
110 clock-names = "cpb-mcasp-auxclk",
111 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
112 "cpb-codec-scki",
113 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
116 transceiver1: can-phy0 {
118 #phy-cells = <0>;
119 max-bitrate = <5000000>;
120 pinctrl-names = "default";
121 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
122 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
123 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
126 transceiver2: can-phy1 {
128 #phy-cells = <0>;
129 max-bitrate = <5000000>;
130 pinctrl-names = "default";
131 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
132 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
135 transceiver3: can-phy2 {
137 #phy-cells = <0>;
138 max-bitrate = <5000000>;
139 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
140 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
143 transceiver4: can-phy3 {
145 #phy-cells = <0>;
146 max-bitrate = <5000000>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
149 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
152 dp_pwr_3v3: regulator-dp-pwr {
153 compatible = "regulator-fixed";
154 regulator-name = "dp-pwr";
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
157 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
158 enable-active-high;
162 compatible = "dp-connector";
164 type = "full-size";
165 dp-pwr-supply = <&dp_pwr_3v3>;
169 remote-endpoint = <&dp0_out>;
176 sw10_button_pins_default: sw10-button-pins-default {
177 pinctrl-single,pins = <
182 main_mmc1_pins_default: main-mmc1-pins-default {
183 pinctrl-single,pins = <
196 vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
197 pinctrl-single,pins = <
202 main_usbss0_pins_default: main-usbss0-pins-default {
203 pinctrl-single,pins = <
209 main_usbss1_pins_default: main-usbss1-pins-default {
210 pinctrl-single,pins = <
215 dp0_pins_default: dp0-pins-default {
216 pinctrl-single,pins = <
221 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
222 pinctrl-single,pins = <
227 main_i2c0_pins_default: main-i2c0-pins-default {
228 pinctrl-single,pins = <
234 main_i2c1_pins_default: main-i2c1-pins-default {
235 pinctrl-single,pins = <
241 main_i2c3_pins_default: main-i2c3-pins-default {
242 pinctrl-single,pins = <
248 main_i2c6_pins_default: main-i2c6-pins-default {
249 pinctrl-single,pins = <
255 mcasp10_pins_default: mcasp10-pins-default {
256 pinctrl-single,pins = <
269 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
270 pinctrl-single,pins = <
275 main_mcan0_pins_default: main-mcan0-pins-default {
276 pinctrl-single,pins = <
282 main_mcan2_pins_default: main-mcan2-pins-default {
283 pinctrl-single,pins = <
289 main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
290 pinctrl-single,pins = <
297 sw11_button_pins_default: sw11-button-pins-default {
298 pinctrl-single,pins = <
303 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
304 pinctrl-single,pins = <
316 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
317 pinctrl-single,pins = <
333 mcu_mdio_pins_default: mcu-mdio1-pins-default {
334 pinctrl-single,pins = <
340 mcu_mcan0_pins_default: mcu-mcan0-pins-default {
341 pinctrl-single,pins = <
347 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
348 pinctrl-single,pins = <
354 mcu_mcan1_pins_default: mcu-mcan1-pins-default {
355 pinctrl-single,pins = <
361 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
362 pinctrl-single,pins = <
374 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
437 non-removable;
438 ti,driver-strength-ohm = <50>;
439 disable-wp;
444 vmmc-supply = <&vdd_mmc1>;
445 vqmmc-supply = <&vdd_sd_dv_alt>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&main_mmc1_pins_default>;
448 ti,driver-strength-ohm = <50>;
449 disable-wp;
458 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
462 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
471 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
472 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
478 cdns,num-lanes = <2>;
479 #phy-cells = <0>;
480 cdns,phy-type = <PHY_TYPE_USB3>;
486 pinctrl-names = "default";
487 pinctrl-0 = <&main_usbss0_pins_default>;
488 ti,vbus-divider;
493 maximum-speed = "super-speed";
495 phy-names = "cdns3,usb3-phy";
499 pinctrl-names = "default";
500 pinctrl-0 = <&main_usbss1_pins_default>;
501 ti,usb2-only;
506 maximum-speed = "high-speed";
510 pinctrl-names = "default";
511 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
514 compatible = "jedec,spi-nor";
516 spi-tx-bus-width = <1>;
517 spi-rx-bus-width = <4>;
518 spi-max-frequency = <40000000>;
519 cdns,tshsl-ns = <60>;
520 cdns,tsd2d-ns = <60>;
521 cdns,tchsh-ns = <60>;
522 cdns,tslch-ns = <60>;
523 cdns,read-delay = <2>;
529 ti,adc-channels = <0 1 2 3 4 5 6 7>;
535 ti,adc-channels = <0 1 2 3 4 5 6 7>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&main_i2c0_pins_default>;
542 clock-frequency = <400000>;
547 gpio-controller;
548 #gpio-cells = <2>;
554 gpio-controller;
555 #gpio-cells = <2>;
557 p09-hog {
558 /* P11 - MCASP/TRACE_MUX_S0 */
559 gpio-hog;
561 output-low;
562 line-name = "MCASP/TRACE_MUX_S0";
565 p10-hog {
566 /* P12 - MCASP/TRACE_MUX_S1 */
567 gpio-hog;
569 output-high;
570 line-name = "MCASP/TRACE_MUX_S1";
576 pinctrl-names = "default";
577 pinctrl-0 = <&main_i2c1_pins_default>;
578 clock-frequency = <400000>;
583 gpio-controller;
584 #gpio-cells = <2>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
587 interrupt-parent = <&main_gpio1>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
601 pinctrl-names = "default";
602 pinctrl-0 = <&main_i2c3_pins_default>;
603 clock-frequency = <400000>;
608 gpio-controller;
609 #gpio-cells = <2>;
612 pcm3168a_1: audio-codec@44 {
616 #sound-dai-cells = <1>;
618 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
620 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
622 clock-names = "scki";
624 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
625 assigned-clocks = <&k3_clks 157 371>;
626 assigned-clock-parents = <&k3_clks 157 400>;
627 assigned-clock-rates = <24576000>; /* for 48KHz */
629 VDD1-supply = <&vsys_3v3>;
630 VDD2-supply = <&vsys_3v3>;
631 VCCAD1-supply = <&vsys_5v0>;
632 VCCAD2-supply = <&vsys_5v0>;
633 VCCDA1-supply = <&vsys_5v0>;
634 VCCDA2-supply = <&vsys_5v0>;
639 pinctrl-names = "default";
640 pinctrl-0 = <&main_i2c6_pins_default>;
641 clock-frequency = <400000>;
646 gpio-controller;
647 #gpio-cells = <2>;
652 pinctrl-names = "default";
653 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
657 phy0: ethernet-phy@0 {
659 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
660 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
665 phy-mode = "rgmii-rxid";
666 phy-handle = <&phy0>;
673 * VP0 - DisplayPort SST
674 * VP1 - DPI0
675 * VP2 - DSI
676 * VP3 - DPI1
679 assigned-clocks = <&k3_clks 152 1>,
683 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
692 remote-endpoint = <&dp0_in>;
698 #address-cells = <1>;
699 #size-cells = <0>;
704 remote-endpoint = <&dpi0_out>;
711 remote-endpoint = <&dp_connector_in>;
757 #sound-dai-cells = <0>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&mcasp10_pins_default>;
762 op-mode = <0>; /* MCASP_IIS_MODE */
763 tdm-slots = <2>;
764 auxclk-fs-ratio = <256>;
766 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
770 tx-num-evt = <0>;
771 rx-num-evt = <0>;
779 clock-frequency = <100000000>;
783 assigned-clocks = <&wiz0_pll1_refclk>;
784 assigned-clock-parents = <&cmn_refclk1>;
788 assigned-clocks = <&wiz0_refclk_dig>;
789 assigned-clock-parents = <&cmn_refclk1>;
793 assigned-clocks = <&wiz1_pll1_refclk>;
794 assigned-clock-parents = <&cmn_refclk1>;
798 assigned-clocks = <&wiz1_refclk_dig>;
799 assigned-clock-parents = <&cmn_refclk1>;
803 assigned-clocks = <&wiz2_pll1_refclk>;
804 assigned-clock-parents = <&cmn_refclk1>;
808 assigned-clocks = <&wiz2_refclk_dig>;
809 assigned-clock-parents = <&cmn_refclk1>;
813 assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
814 assigned-clock-parents = <&wiz0_pll1_refclk>;
818 cdns,num-lanes = <1>;
819 #phy-cells = <0>;
820 cdns,phy-type = <PHY_TYPE_PCIE>;
826 assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
827 assigned-clock-parents = <&wiz1_pll1_refclk>;
831 cdns,num-lanes = <2>;
832 #phy-cells = <0>;
833 cdns,phy-type = <PHY_TYPE_PCIE>;
839 assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
840 assigned-clock-parents = <&wiz2_pll1_refclk>;
844 cdns,num-lanes = <2>;
845 #phy-cells = <0>;
846 cdns,phy-type = <PHY_TYPE_PCIE>;
855 cdns,phy-type = <PHY_TYPE_DP>;
856 cdns,num-lanes = <4>;
857 cdns,max-bit-rate = <5400>;
858 #phy-cells = <0>;
864 phy-names = "dpphy";
865 pinctrl-names = "default";
866 pinctrl-0 = <&dp0_pins_default>;
870 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
872 phy-names = "pcie-phy";
873 num-lanes = <1>;
877 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
879 phy-names = "pcie-phy";
880 num-lanes = <2>;
884 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
886 phy-names = "pcie-phy";
887 num-lanes = <2>;
892 phy-names = "pcie-phy";
893 num-lanes = <1>;
899 phy-names = "pcie-phy";
900 num-lanes = <2>;
906 phy-names = "pcie-phy";
907 num-lanes = <2>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&mcu_mcan0_pins_default>;
934 pinctrl-names = "default";
935 pinctrl-0 = <&mcu_mcan1_pins_default>;
940 pinctrl-names = "default";
941 pinctrl-0 = <&main_mcan0_pins_default>;
950 pinctrl-names = "default";
951 pinctrl-0 = <&main_mcan2_pins_default>;