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Searched +full:npcm750 +full:- +full:reset (Results 1 – 15 of 15) sorted by relevance

/Linux-v6.1/arch/arm64/boot/dts/nuvoton/
Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16 compatible = "simple-bus";
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/Linux-v6.1/Documentation/devicetree/bindings/reset/
Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
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/Linux-v6.1/arch/arm/boot/dts/
Dnuvoton-common-npcm7xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <25000000>;
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Dnuvoton-npcm750-runbmc-olympus.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
6 #include "nuvoton-npcm750.dtsi"
7 #include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi"
9 #include <dt-bindings/i2c/i2c.h>
10 #include <dt-bindings/gpio/gpio.h>
13 model = "Nuvoton npcm750 RunBMC Olympus";
14 compatible = "nuvoton,npcm750";
43 stdout-path = &serial3;
50 iio-hwmon {
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Dnuvoton-npcm730-gbs.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
5 #include "nuvoton-npcm730.dtsi"
6 #include <dt-bindings/gpio/gpio.h>
10 compatible = "quanta,gbs-bmc","nuvoton,npcm730";
71 stdout-path = &serial0;
78 gpio-keys {
79 compatible = "gpio-keys";
80 sas-cable0 {
81 label = "sas-cable0";
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/Linux-v6.1/Documentation/devicetree/bindings/iio/adc/
Dnuvoton,npcm750-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nuvoton,npcm750-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The NPCM7XX ADC is a 10-bit converter and NPCM8XX ADC is a 12-bit converter,
19 - nuvoton,npcm750-adc
20 - nuvoton,npcm845-adc
36 vref-supply:
39 "#io-channel-cells":
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/Linux-v6.1/Documentation/devicetree/bindings/spi/
Dnuvoton,npcm-pspi.txt6 - compatible : "nuvoton,npcm750-pspi" for Poleg NPCM7XX.
7 "nuvoton,npcm845-pspi" for Arbel NPCM8XX.
8 - #address-cells : should be 1. see spi-bus.txt
9 - #size-cells : should be 0. see spi-bus.txt
10 - specifies physical base address and size of the register.
11 - interrupts : contain PSPI interrupt.
12 - clocks : phandle of PSPI reference clock.
13 - clock-names: Should be "clk_apb5".
14 - pinctrl-names : a pinctrl state named "default" must be defined.
15 - pinctrl-0 : phandle referencing pin configuration of the device.
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/Linux-v6.1/drivers/reset/
Dreset-npcm.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/reset-controller.h>
36 /* NPCM7xx Reset registers */
104 writel(NPCM_SWRST << rc->sw_reset_number, rc->base + NPCM_SWRSTR); in npcm_rc_restart()
121 spin_lock_irqsave(&rc->lock, flags); in npcm_rc_setclear_reset()
122 stat = readl(rc->base + ctrl_offset); in npcm_rc_setclear_reset()
124 writel(stat | rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
126 writel(stat & ~rst_bit, rc->base + ctrl_offset); in npcm_rc_setclear_reset()
127 spin_unlock_irqrestore(&rc->lock, flags); in npcm_rc_setclear_reset()
150 return (readl(rc->base + ctrl_offset) & rst_bit); in npcm_rc_status()
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/Linux-v6.1/drivers/watchdog/
Dnpcm_wdt.c1 // SPDX-License-Identifier: GPL-2.0
23 #define NPCM_WTRF BIT(2) /* Reset flag */
24 #define NPCM_WTRE BIT(1) /* Reset enable */
25 #define NPCM_WTR BIT(0) /* Reset counter */
60 val = readl(wdt->reg); in npcm_wdt_ping()
61 writel(val | NPCM_WTR, wdt->reg); in npcm_wdt_ping()
71 if (wdt->clk) in npcm_wdt_start()
72 clk_prepare_enable(wdt->clk); in npcm_wdt_start()
74 if (wdd->timeout < 2) in npcm_wdt_start()
76 else if (wdd->timeout < 3) in npcm_wdt_start()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
51 bool "Update boot-enabled watchdog until userspace takes over"
77 bool "Enable watchdog hrtimer-based pretimeouts"
178 to toggle reset line if SoC fails to ping watchdog via GPIO.
190 cause system reset.
228 tristate "Watchdog device controlled through GPIO-line"
233 controlled through GPIO-line.
287 the watchdog triggers the system will be reset.
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/Linux-v6.1/drivers/iio/adc/
Dnpcm_adc.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/reset.h>
35 struct reset_control *reset; member
106 regtemp = ioread32(info->regs + NPCM_ADCCON); in npcm_adc_isr()
108 iowrite32(regtemp, info->regs + NPCM_ADCCON); in npcm_adc_isr()
109 wake_up_interruptible(&info->wq); in npcm_adc_isr()
110 info->int_status = true; in npcm_adc_isr()
122 regtemp = ioread32(info->regs + NPCM_ADCCON); in npcm_adc_read()
124 info->int_status = false; in npcm_adc_read()
126 NPCM_ADCCON_ADC_CONV, info->regs + NPCM_ADCCON); in npcm_adc_read()
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/Linux-v6.1/drivers/spi/
Dspi-npcm-pspi.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset.h>
22 struct reset_control *reset; member
37 #define DRIVER_NAME "npcm-pspi"
70 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
72 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_enable()
79 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
81 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_irq_disable()
88 val = ioread16(priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
90 iowrite16(val, priv->base + NPCM_PSPI_CTL1); in npcm_pspi_enable()
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/Linux-v6.1/drivers/tty/serial/8250/
D8250_of.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/reset.h>
36 struct device_node *np = ofdev->dev.of_node; in of_platform_serial_setup()
37 struct uart_port *port = &up->port; in of_platform_serial_setup()
43 pm_runtime_enable(&ofdev->dev); in of_platform_serial_setup()
44 pm_runtime_get_sync(&ofdev->dev); in of_platform_serial_setup()
46 if (of_property_read_u32(np, "clock-frequency", &clk)) { in of_platform_serial_setup()
49 info->clk = devm_clk_get(&ofdev->dev, NULL); in of_platform_serial_setup()
50 if (IS_ERR(info->clk)) { in of_platform_serial_setup()
51 ret = PTR_ERR(info->clk); in of_platform_serial_setup()
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/Linux-v6.1/drivers/hwmon/
Dnpcm750-pwm-fan.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
150 * 320RPM/pulse 2, ...-- 10.6Hz)
154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
220 mutex_lock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
223 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); in npcm7xx_pwm_config_set()
224 tmp_buf = ioread32(NPCM7XX_PWM_REG_CR(data->pwm_base, module)); in npcm7xx_pwm_config_set()
244 mutex_unlock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
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/Linux-v6.1/drivers/i2c/busses/
Di2c-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
142 #define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
145 #define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
146 #define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
147 #define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
343 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
349 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); in npcm_i2c_select_bank()
354 bus->stop_ind = I2C_NO_STATUS_IND; in npcm_i2c_init_params()
355 bus->rd_size = 0; in npcm_i2c_init_params()
356 bus->wr_size = 0; in npcm_i2c_init_params()
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