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/Linux-v5.10/Documentation/devicetree/bindings/arm/
Dsecure.txt1 * ARM Secure world bindings
4 "Normal" and "Secure". Most devicetree consumers (including the Linux
6 world or the Secure world. However some devicetree consumers are
8 visible only in the Secure address space, only in the Normal address
10 virtual machine which boots Secure firmware and wants to tell the
13 The general principle of the naming scheme for Secure world bindings
14 is that any property that needs a different value in the Secure world
15 can be supported by prefixing the property name with "secure-". So for
16 instance "secure-foo" would override "foo". For property names with
17 a vendor prefix, the Secure variant of "vendor,foo" would be
[all …]
Dpmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - arm,armv8-pmuv3 # Only for s/w models
24 - arm,arm1136-pmu
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Djuno,scpi.txt5 ------------------------------------
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
10 Each sub-node represents the reserved area for SCPI.
12 Required sub-node properties:
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
18 --------------------------------------------------------------
20 - compatible : should be "arm,scpi-sensors".
21 - #thermal-sensor-cells: should be set to 1.
/Linux-v5.10/Documentation/devicetree/bindings/iommu/
Dqcom,iommu.txt3 Qualcomm "B" family devices which are not compatible with arm-smmu have
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
14 Followed by "qcom,msm-iommu-v1".
16 - clock-names : Should be a pair of "iface" (required for IOMMUs
20 - clocks : Phandles for respective clocks described by
21 clock-names.
23 - #address-cells : must be 1.
25 - #size-cells : must be 1.
[all …]
Dmsm,iommu-v0.txt5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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/Linux-v5.10/Documentation/devicetree/bindings/nvmem/
Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data bindings
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@st.com>
19 - $ref: "nvmem.yaml#"
24 - st,stm32f4-otp
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/Linux-v5.10/arch/arm/common/
Dsecure_cntvoff.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Initialization of CNTVOFF register from secure mode
13 .arch armv7-a
15 * CNTVOFF has to be initialized either from non-secure Hypervisor
16 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
17 * then it should be handled by the secure code. The CPU must implement
21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
23 mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
/Linux-v5.10/arch/arm/mach-omap2/
Domap-secure.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP Secure API infrastructure.
11 #include <linux/arm-smccc.h>
22 #include "omap-secure.h"
37 * We only check that the OP-TEE node is present and available. The in omap_optee_init_check()
38 * OP-TEE kernel driver is not needed for the type of interaction made in omap_optee_init_check()
39 * with OP-TEE here so the driver's status is not checked. in omap_optee_init_check()
48 * omap_sec_dispatcher: Routine to dispatch low power secure
53 * @arg1, arg2, arg3 args4: Parameters passed to secure API
55 * Return the non-zero error value on failure.
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Domap-headsmp.S1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2009-2014 Texas Instruments, Inc.
58 .arch armv7-a
110 * CortexA9 r1pX and r2pX. The Control Register secure
112 * bit 0 == Secure Enable
113 * bit 1 == Non-Secure Enable
114 * The Non-Secure banked register has not changed
116 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
120 * 2) CPU1 must re-enable the GIC distributor on
Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
116 * by ROM code in "secure world" using the smc call and there is no
150 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA in omap4_secondary_init()
151 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
153 * OMAP443X GP devices- SMP bit isn't accessible. in omap4_secondary_init()
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/Linux-v5.10/drivers/tee/optee/
Doptee_smc.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
8 #include <linux/arm-smccc.h>
28 * Normal cached memory (write-back), shareable for SMP systems and not
36 * 32-bit registers.
44 * 65cb6b93-af0c-4617-8ed6-644a8d1140f8
75 * Used by non-secure world to figure out which Trusted OS is installed.
78 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
88 * Used by non-secure world to figure out which version of the Trusted OS
92 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
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Doptee_msg.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
3 * Copyright (c) 2015-2019, Linaro Limited
12 * This file defines the OP-TEE message protocol used to communicate
13 * with an instance of OP-TEE running in secure world.
18 * 3. Requests from secure world, Remote Procedure Call (RPC), handled by
19 * tee-supplicant.
23 * Part 1 - formatting of messages
40 * Meta parameter to be absorbed by the Secure OS and not passed
48 * Pointer to a list of pages used to register user-defined SHM buffer.
51 * list of page addresses. OP-TEE core can reconstruct contiguous buffer from
[all …]
/Linux-v5.10/Documentation/devicetree/bindings/arm/samsung/
Dsamsung-secure-firmware.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/samsung/samsung-secure-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos Secure Firmware
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - const: samsung,secure-firmware
19 Address of non-secure SYSRAM used for communication with firmware.
23 - compatible
24 - reg
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/Linux-v5.10/drivers/vfio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
23 tristate "VFIO Non-Privileged userspace driver framework"
27 VFIO provides a framework for secure userspace device drivers.
28 See Documentation/driver-api/vfio.rst for more details.
33 bool "VFIO No-IOMMU support"
38 considered secure. VFIO No-IOMMU mode enables IOMMU groups for
39 devices without IOMMU backing for the purpose of re-using the VFIO
40 infrastructure in a non-secure mode. Use of this mode will result
50 source "drivers/vfio/fsl-mc/Kconfig"
/Linux-v5.10/Documentation/devicetree/bindings/soc/rockchip/
Dgrf.txt7 - GRF, used for general non-secure system,
8 - SGRF, used for general secure system,
9 - PMUGRF, used for always on system
14 - GRF, used for general non-secure system,
15 - SGRF, used for general secure system,
16 - DETECTGRF, used for audio codec system,
17 - COREGRF, used for pvtm,
21 - compatible: GRF should be one of the following:
22 - "rockchip,px30-grf", "syscon": for px30
23 - "rockchip,rk3036-grf", "syscon": for rk3036
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/Linux-v5.10/Documentation/devicetree/bindings/mailbox/
Darm,mhu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
19 be a 'Secure' resource, hence can't be used by Linux running NS.
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
38 - arm,mhu-doorbell
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/Linux-v5.10/drivers/staging/wfx/
Dhif_rx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Implementation of chip-to-host event (aka indications) of WFxxx Split Mac
6 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
7 * Copyright (c) 2010, ST-Ericsson
25 int cmd = hif->id; in hif_generic_confirm()
26 int len = le16_to_cpu(hif->len) - 4; // drop header in hif_generic_confirm()
28 WARN(!mutex_is_locked(&wdev->hif_cmd.lock), "data locking error"); in hif_generic_confirm()
30 if (!wdev->hif_cmd.buf_send) { in hif_generic_confirm()
31 dev_warn(wdev->dev, "unexpected confirmation: 0x%.2x\n", cmd); in hif_generic_confirm()
32 return -EINVAL; in hif_generic_confirm()
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/Linux-v5.10/Documentation/devicetree/bindings/misc/
Dbrcm,kona-smc.txt1 Broadcom Secure Monitor Bounce buffer
2 -----------------------------------------------------
4 used for non-secure to secure communications.
7 - compatible : "brcm,kona-smc"
8 - DEPRECATED: compatible : "bcm,kona-smc"
9 - reg : Location and size of bounce buffer
13 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
/Linux-v5.10/Documentation/arm/samsung/
Dbootloader-interface.rst14 In the document "boot loader" means any of following: U-boot, proprietary
19 1. Non-Secure mode
37 2. Secure mode
65 3. Other (regardless of secure/non-secure mode)
72 0x0908 Non-zero Secondary CPU boot up indicator
79 AFTR - ARM Off Top Running, a low power mode, Cortex cores and many other
81 MCPM - Multi-Cluster Power Management
/Linux-v5.10/Documentation/arm64/
Dbooting.rst13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
15 mode. EL3 is the highest priority level and exists only in secure mode.
19 is passed to the Linux kernel. This may include secure monitor and
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
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/Linux-v5.10/drivers/irqchip/
Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
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/Linux-v5.10/Documentation/powerpc/
Dultravisor.rst1 .. SPDX-License-Identifier: GPL-2.0
15 POWER 9 that enables Secure Virtual Machines (SVMs). DD2.3 chips
16 (PVR=0x004e1203) or greater will be PEF-capable. A new ISA release
25 +------------------+
29 +------------------+
31 +------------------+
33 +------------------+
35 +------------------+
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
[all …]
/Linux-v5.10/drivers/rtc/
Drtc-mxc_v2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
22 #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
51 * The caller should hold the pdata->lock
63 if (!--timeout) { in mxc_rtc_sync_lp_locked()
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/Linux-v5.10/arch/powerpc/kvm/
Dbook3s_hv_uvmem.c1 // SPDX-License-Identifier: GPL-2.0
3 * Secure pages management: Migration of pages between normal and secure
10 * A pseries guest can be run as secure guest on Ultravisor-enabled
13 * hypervisor (HV) and secure memory managed by Ultravisor (UV).
15 * The page-in or page-out requests from UV will come to HV as hcalls and
18 * Private ZONE_DEVICE memory equal to the amount of secure memory
19 * available in the platform for running secure guests is hotplugged.
20 * Whenever a page belonging to the guest becomes secure, a page from this
21 * private device memory is used to represent and track that secure page
31 * kvm->arch.uvmem_lock is a per-guest lock that prevents concurrent
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