| /Linux-v5.4/include/linux/mtd/ |
| D | nand.h | 17 * @bits_per_cell: number of bits per NAND cell
25 * @ntargets: total number of targets exposed by the NAND device
65 * struct nand_pos - NAND position object
66 * @target: the NAND target/die
84 * struct nand_page_io_req - NAND I/O request object
94 * This object is used to pass per-page I/O requests to NAND sub-layers. This
96 * specific NAND layers can focus on translating these information into
117 * struct nand_ecc_req - NAND ECC requirements
139 * struct nand_ops - NAND operations
141 * erasing, this has been taken care of by the generic NAND layer
[all …]
|
| /Linux-v5.4/drivers/mtd/nand/raw/ |
| D | Kconfig | 6 bool "NAND ECC Smart Media byte order"
14 tristate "Raw/Parallel NAND Device Support"
20 NAND flash devices. For further information see
21 <http://www.linux-mtd.infradead.org/doc/nand.html>.
32 ECC codes. They are used with NAND devices requiring more than 1 bit
35 comment "Raw/parallel NAND flash controllers"
41 tristate "Denali NAND controller on Intel Moorestown"
45 Enable the driver for NAND flash on Intel Moorestown, using the
46 Denali NAND controller core.
49 tristate "Denali NAND controller as a DT device"
[all …]
|
| D | nand_ids.c | 25 * Some incompatible NAND chips share device ID's and so must be
56 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
57 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
58 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
59 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xD6, 8, SZ_8K, SP_OPTIONS),
60 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xE6, 8, SZ_8K, SP_OPTIONS),
62 LEGACY_ID_NAND("NAND 16MiB 1,8V 8-bit", 0x33, 16, SZ_16K, SP_OPTIONS),
63 LEGACY_ID_NAND("NAND 16MiB 3,3V 8-bit", 0x73, 16, SZ_16K, SP_OPTIONS),
64 LEGACY_ID_NAND("NAND 16MiB 1,8V 16-bit", 0x43, 16, SZ_16K, SP_OPTIONS16),
65 LEGACY_ID_NAND("NAND 16MiB 3,3V 16-bit", 0x53, 16, SZ_16K, SP_OPTIONS16),
[all …]
|
| D | meson_nand.c | 3 * Amlogic Meson Nand Flash Controller Driver
91 /* nand flash controller delay 3 ns */
109 struct nand_chip nand; member
217 static struct meson_nfc_nand_chip *to_meson_nand(struct nand_chip *nand) in to_meson_nand() argument
219 return container_of(nand, struct meson_nfc_nand_chip, nand); in to_meson_nand()
222 static void meson_nfc_select_chip(struct nand_chip *nand, int chip) in meson_nfc_select_chip() argument
224 struct meson_nfc_nand_chip *meson_chip = to_meson_nand(nand); in meson_nfc_select_chip()
225 struct meson_nfc *nfc = nand_get_controller_data(nand); in meson_nfc_select_chip()
265 static void meson_nfc_cmd_access(struct nand_chip *nand, int raw, bool dir, in meson_nfc_cmd_access() argument
268 struct mtd_info *mtd = nand_to_mtd(nand); in meson_nfc_cmd_access()
[all …]
|
| D | sunxi_nand.c | 161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
181 * struct sunxi_nand_chip - stores NAND chip device related information
183 * @node: used to store NAND chips into a list
184 * @nand: base NAND chip structure
185 * @clk_rate: clk_rate required for this NAND chip
186 * @timing_cfg: TIMING_CFG register value for this NAND chip
187 * @timing_ctl: TIMING_CTL register value for this NAND chip
188 * @nsels: number of CS lines required by the NAND chip
193 struct nand_chip nand; member
[all …]
|
| /Linux-v5.4/drivers/mtd/nand/ |
| D | core.c | 10 #define pr_fmt(fmt) "nand: " fmt
13 #include <linux/mtd/nand.h>
17 * @nand: NAND device
22 bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos) in nanddev_isbad() argument
24 if (nanddev_bbt_is_initialized(nand)) { in nanddev_isbad()
28 entry = nanddev_bbt_pos_to_entry(nand, pos); in nanddev_isbad()
29 status = nanddev_bbt_get_block_status(nand, entry); in nanddev_isbad()
32 if (nand->ops->isbad(nand, pos)) in nanddev_isbad()
37 nanddev_bbt_set_block_status(nand, entry, status); in nanddev_isbad()
47 return nand->ops->isbad(nand, pos); in nanddev_isbad()
[all …]
|
| D | bbt.c | 10 #define pr_fmt(fmt) "nand-bbt: " fmt
12 #include <linux/mtd/nand.h>
17 * @nand: NAND device
23 int nanddev_bbt_init(struct nand_device *nand) in nanddev_bbt_init() argument
26 unsigned int nblocks = nanddev_neraseblocks(nand); in nanddev_bbt_init()
30 nand->bbt.cache = kcalloc(nwords, sizeof(*nand->bbt.cache), in nanddev_bbt_init()
32 if (!nand->bbt.cache) in nanddev_bbt_init()
41 * @nand: NAND device
45 void nanddev_bbt_cleanup(struct nand_device *nand) in nanddev_bbt_cleanup() argument
47 kfree(nand->bbt.cache); in nanddev_bbt_cleanup()
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/mtd/ |
| D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC)
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
16 - interrupts: shall define the NAND controller interrupt.
[all …]
|
| D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller
3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
19 the core NAND controller, of the following form:
33 - reg : the register start and length for NAND register region.
35 (optional) NAND flash cache range (if at non-standard offset)
37 ranges. Should contain "nand" and (optionally)
38 "flash-dma" and/or "nand-cache".
39 - interrupts : The NAND CTLRDY interrupt and (if Flash DMA is available)
43 May be "nand", if the SoC has the individual NAND
50 - clock : reference to the clock for the NAND controller
[all …]
|
| D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller
5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
18 Individual NAND chips are children of the NAND controller node. Currently
19 only one NAND chip supported.
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
[all …]
|
| D | atmel-nand.txt | 1 Atmel NAND flash controller bindings
3 The NAND flash controller node should be defined under the EBI bus (see
5 One or several NAND devices can be defined under this NAND controller.
6 The NAND controller might be connected to an ECC engine.
8 * NAND controller bindings:
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
[all …]
|
| D | qcom_nandc.txt | 1 * Qualcomm NAND controller
5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
20 NAND. Refer to dma.txt and qcom_adm.txt for more details
23 number specified for the NAND controller on the given
26 number specified for the NAND controller on the given
31 and the channel number to be used for NAND. Refer to
37 * NAND chip-select
40 chip-selects which (may) contain NAND flash chips. Their properties are as
[all …]
|
| D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC)
3 This variant of the Freescale NAND flash controller (NFC) can be found on
10 - #address-cells: shall be set to 1. Encode the nand CS.
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
14 rate and should not exceed maximum timing for any NAND memory chip
15 in a board stuffing. Typical NAND memory timings derived from this
23 Children nodes represent the available nand chips. Currently the driver can
24 only handle one NAND chip.
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
[all …]
|
| D | ingenic,jz4780-nand.txt | 1 * Ingenic JZ4780 NAND/ECC
3 This file documents the device tree bindings for NAND flash devices on the
4 JZ4780. NAND devices are connected to the NEMC controller (described in
5 memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
8 Required NAND controller device properties:
10 * ingenic,jz4740-nand
11 * ingenic,jz4725b-nand
12 * ingenic,jz4780-nand
13 - reg: For each bank with a NAND chip attached, should specify a bank number,
16 Optional NAND controller device properties:
[all …]
|
| D | denali-nand.txt | 1 * Denali NAND controller
5 "altr,socfpga-denali-nand" - for Altera SOCFPGA
6 "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a)
7 "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b)
15 - clock-names: should contain "nand", "nand_x", "ecc"
18 Sub-nodes represent available NAND chips.
25 - nand-ecc-step-size: see nand-controller.yaml for details.
27 512 for "altr,socfpga-denali-nand"
28 1024 for "socionext,uniphier-denali-nand-v5a"
29 1024 for "socionext,uniphier-denali-nand-v5b"
[all …]
|
| D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller
5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
[all …]
|
| D | nand-controller.yaml | 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
31 pattern: "^nand-controller(@.*)?"
42 "^nand@[a-f0-9]$":
49 nand-ecc-mode:
55 embedded in the NAND controller) or software correction
57 and should be replaced by soft and nand-ecc-algo.
[all …]
|
| D | stm32-fmc2-nand.txt | 2 NAND Interface
7 - reg: NAND flash controller memory areas.
14 - clocks: The clock needed by the NAND flash controller
21 * NAND device bindings:
24 - reg: describes the CS lines assigned to the NAND device.
27 - nand-on-flash-bbt: see nand-controller.yaml
28 - nand-ecc-strength: see nand-controller.yaml
29 - nand-ecc-step-size: see nand-controller.yaml
32 - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Hamming)
33 - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
[all …]
|
| D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding
7 NAND controller's registers. The second contains base
8 physical address and size of NAND controller's buffer.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
[all …]
|
| D | fsmc-nand.txt | 2 NAND Interface
5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
[all …]
|
| D | davinci-nand.txt | 1 Device tree bindings for Texas instruments Davinci/Keystone NAND controller
4 NAND interface contains.
12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
22 for accessing the nand.
29 address for the chip select space the NAND Flash
35 address for the chip select space the NAND Flash
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
50 - nand-bus-width: buswidth 8 or 16. If not present 8.
52 - nand-on-flash-bbt: use flash based bad block table support. OOB
[all …]
|
| D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding
3 This file documents the device tree bindings for MTK SoCs NAND controllers.
5 the nand controller interface driver and the ECC engine driver.
10 1) NFC NAND Controller Interface (NFI):
13 The first part of NFC is NAND Controller Interface (NFI) HW.
24 - #address-cells: NAND chip index, should be 1.
42 - children nodes: NAND chips.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
[all …]
|
| /Linux-v5.4/drivers/mtd/nand/spi/ |
| D | core.c | 10 #define pr_fmt(fmt) "spi-nand: " fmt
52 struct nand_device *nand = spinand_to_nand(spinand); in spinand_get_cfg() local
55 spinand->cur_target >= nand->memorg.ntargets)) in spinand_get_cfg()
64 struct nand_device *nand = spinand_to_nand(spinand); in spinand_set_cfg() local
68 spinand->cur_target >= nand->memorg.ntargets)) in spinand_set_cfg()
108 * spinand_select_target() - Select a specific NAND target/die
118 struct nand_device *nand = spinand_to_nand(spinand); in spinand_select_target() local
121 if (WARN_ON(target >= nand->memorg.ntargets)) in spinand_select_target()
127 if (nand->memorg.ntargets == 1) { in spinand_select_target()
142 struct nand_device *nand = spinand_to_nand(spinand); in spinand_init_cfg_cache() local
[all …]
|
| /Linux-v5.4/drivers/mtd/nand/raw/atmel/ |
| D | nand-controller.c | 13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
30 * Add Nand Flash Controller support for SAMA5 SoC
201 struct atmel_nand *nand);
203 int (*setup_data_interface)(struct atmel_nand *nand, int csline,
334 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n"); in atmel_nfc_wait()
419 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_read_byte() local
421 return ioread8(nand->activecs->io.virt); in atmel_nand_read_byte()
426 struct atmel_nand *nand = to_atmel_nand(chip); in atmel_nand_write_byte() local
429 iowrite16(byte | (byte << 8), nand->activecs->io.virt); in atmel_nand_write_byte()
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 51 ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
62 ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy,
63 nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6,
83 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
94 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
106 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
120 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
121 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
122 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
|
