Searched +full:nand +full:- +full:controller (Results 1 – 25 of 515) sorted by relevance
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/Linux-v5.10/drivers/mtd/nand/raw/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 6 bool "NAND ECC Smart Media byte order" 14 tristate "Raw/Parallel NAND Device Support" 20 NAND flash devices. For further information see 21 <http://www.linux-mtd.infradead.org/doc/nand.html>. 32 ECC codes. They are used with NAND devices requiring more than 1 bit 35 comment "Raw/parallel NAND flash controllers" 41 tristate "Denali NAND controller on Intel Moorestown" 45 Enable the driver for NAND flash on Intel Moorestown, using the 46 Denali NAND controller core. [all …]
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D | sunxi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * https://github.com/yuq/sunxi-nfc-mtd 9 * https://github.com/hno/Allwinner-Info 16 #include <linux/dma-mapping.h> 70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8) 107 #define NFC_ADR_NUM(x) (((x) - 1) << 16) 161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select 163 * @cs: the NAND CS id used to communicate with a NAND Chip 164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC 172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support [all …]
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D | cs553x_nand.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 * This is a device driver for the NAND flash controller found on 11 * mtd-id for command line partitioning is cs553x_nand_cs[0-3] 12 * where 0-3 reflects the chip select for NAND. 34 /* NAND Timing MSRs */ 35 #define MSR_NANDF_DATA 0x5140001b /* NAND Flash Data Timing MSR */ 36 #define MSR_NANDF_CTL 0x5140001c /* NAND Flash Control Timing */ 39 /* NAND BAR MSRs */ 46 #define FLSH_NOR_NAND (1ULL<<33) /* 1 for NAND */ 55 /* Registers within the NAND flash controller BAR -- memory mapped */ [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/mtd/ |
D | marvell-nand.txt | 1 Marvell NAND Flash Controller (NFC) 4 - compatible: can be one of the following: 5 * "marvell,armada-8k-nand-controller" 6 * "marvell,armada370-nand-controller" 7 * "marvell,pxa3xx-nand-controller" 8 * "marvell,armada-8k-nand" (deprecated) 9 * "marvell,armada370-nand" (deprecated) 10 * "marvell,pxa3xx-nand" (deprecated) 13 - reg: NAND flash controller memory area. 14 - #address-cells: shall be set to 1. Encode the NAND CS. [all …]
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D | brcm,brcmnand.txt | 1 * Broadcom STB NAND Controller 3 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND 4 flash chips. It has a memory-mapped register interface for both control 5 registers and for its data input/output buffer. On some SoCs, this controller is 9 This controller was originally designed for STB SoCs (BCM7xxx) but is now 15 - compatible : May contain an SoC-specific compatibility string (see below) 16 to account for any SoC-specific hardware bits that may be 17 added on top of the base core controller. 19 the core NAND controller, of the following form: 21 string, like "brcm,brcmnand-v7.0" [all …]
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D | qcom_nandc.txt | 1 * Qualcomm NAND controller 4 - compatible: must be one of the following: 5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x 7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in 9 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in 12 - reg: MMIO address range 13 - clocks: must contain core clock and always on clock 14 - clock-names: must contain "core" for the core clock and "aon" for the 18 - dmas: DMA specifier, consisting of a phandle to the ADM DMA 19 controller node and the channel number to be used for [all …]
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D | atmel-nand.txt | 1 Atmel NAND flash controller bindings 3 The NAND flash controller node should be defined under the EBI bus (see 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt). 5 One or several NAND devices can be defined under this NAND controller. 6 The NAND controller might be connected to an ECC engine. 8 * NAND controller bindings: 11 - compatible: should be one of the following 12 "atmel,at91rm9200-nand-controller" 13 "atmel,at91sam9260-nand-controller" 14 "atmel,at91sam9261-nand-controller" [all …]
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D | nvidia-tegra20-nand.txt | 1 NVIDIA Tegra NAND Flash controller 4 - compatible: Must be one of: 5 - "nvidia,tegra20-nand" 6 - reg: MMIO address range 7 - interrupts: interrupt output of the NFC controller 8 - clocks: Must contain an entry for each entry in clock-names. 9 See ../clocks/clock-bindings.txt for details. 10 - clock-names: Must include the following entries: 11 - nand 12 - resets: Must contain an entry for each entry in reset-names. [all …]
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D | nand-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NAND Chip and NAND Controller Generic Binding 10 - Miquel Raynal <miquel.raynal@bootlin.com> 11 - Richard Weinberger <richard@nod.at> 14 The NAND controller should be represented with its own DT node, and 15 all NAND chips attached to this controller should be defined as 16 children nodes of the NAND controller. This representation should be [all …]
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D | samsung-s3c2410.txt | 1 * Samsung S3C2410 and compatible NAND flash controller 4 - compatible : The possible values are: 5 "samsung,s3c2410-nand" 6 "samsung,s3c2412-nand" 7 "samsung,s3c2440-nand" 8 - reg : register's location and length. 9 - #address-cells, #size-cells : see nand-controller.yaml 10 - clocks : phandle to the nand controller clock 11 - clock-names : must contain "nand" 14 Child nodes representing the available nand chips. [all …]
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D | vf610-nfc.txt | 1 Freescale's NAND flash controller (NFC) 3 This variant of the Freescale NAND flash controller (NFC) can be found on 7 - compatible: Should be set to "fsl,vf610-nfc". 8 - reg: address range of the NFC. 9 - interrupts: interrupt of the NFC. 10 - #address-cells: shall be set to 1. Encode the nand CS. 11 - #size-cells : shall be set to 0. 12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>; 13 - assigned-clock-rates: The NAND bus timing is derived from this clock 14 rate and should not exceed maximum timing for any NAND memory chip [all …]
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D | denali,nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/mtd/denali,nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Denali NAND controller 10 - Masahiro Yamada <yamada.masahiro@socionext.com> 15 - altr,socfpga-denali-nand 16 - socionext,uniphier-denali-nand-v5a 17 - socionext,uniphier-denali-nand-v5b 19 reg-names: [all …]
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D | mxic-nand.txt | 1 Macronix Raw NAND Controller Device Tree Bindings 2 ------------------------------------------------- 5 - compatible: should be "mxic,multi-itfc-v009-nand-controller" 6 - reg: should contain 1 entry for the registers 7 - #address-cells: should be set to 1 8 - #size-cells: should be set to 0 9 - interrupts: interrupt line connected to this raw NAND controller 10 - clock-names: should contain "ps", "send" and "send_dly" 11 - clocks: should contain 3 phandles for the "ps", "send" and 15 - children nodes represent the available NAND chips. [all …]
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D | cadence-nand-controller.txt | 1 * Cadence NAND controller 4 - compatible : "cdns,hp-nfc" 5 - reg : Contains two entries, each of which is a tuple consisting of a 7 length of the controller register set. The second entry is the 9 - reg-names: should contain "reg" and "sdma" 10 - #address-cells: should be 1. The cell encodes the chip select connection. 11 - #size-cells : should be 0. 12 - interrupts : The interrupt number. 13 - clocks: phandle of the controller core clock (nf_clk). 16 - dmas: shall reference DMA channel associated to the NAND controller [all …]
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D | mtk-nand.txt | 1 MTK SoCs NAND FLASH controller (NFC) DT binding 3 This file documents the device tree bindings for MTK SoCs NAND controllers. 4 The functional split of the controller requires two drivers to operate: 5 the nand controller interface driver and the ECC engine driver. 10 1) NFC NAND Controller Interface (NFI): 13 The first part of NFC is NAND Controller Interface (NFI) HW. 15 - compatible: Should be one of 16 "mediatek,mt2701-nfc", 17 "mediatek,mt2712-nfc", 18 "mediatek,mt7622-nfc". [all …]
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D | hisi504-nand.txt | 1 Hisilicon Hip04 Soc NAND controller DT binding 5 - compatible: Should be "hisilicon,504-nfc". 6 - reg: The first contains base physical address and size of 7 NAND controller's registers. The second contains base 8 physical address and size of NAND controller's buffer. 9 - interrupts: Interrupt number for nfc. 10 - nand-bus-width: See nand-controller.yaml. 11 - nand-ecc-mode: Support none and hw ecc mode. 12 - #address-cells: Partition address, should be set 1. 13 - #size-cells: Partition size, should be set 1. [all …]
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D | arasan,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/arasan,nand-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Arasan NAND Flash Controller with ONFI 3.1 support device tree bindings 10 - $ref: "nand-controller.yaml" 13 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> 18 - enum: 19 - xlnx,zynqmp-nand-controller 20 - const: arasan,nfc-v3p10 [all …]
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D | tango-nand.txt | 1 Sigma Designs Tango4 NAND Flash Controller (NFC) 5 - compatible: "sigma,smp8758-nand" 6 - reg: address/size of nfc_reg, nfc_mem, and pbus_reg 7 - dmas: reference to the DMA channel used by the controller 8 - dma-names: "rxtx" 9 - clocks: reference to the system clock 10 - #address-cells: <1> 11 - #size-cells: <0> 13 Children nodes represent the available NAND chips. 14 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings. [all …]
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D | fsmc-nand.txt | 1 ST Microelectronics Flexible Static Memory Controller (FSMC) 2 NAND Interface 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand" 6 - reg : Address range of the mtd chip 7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd" 10 - bank-width : Width (in bytes) of the device. If not present, the width 12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped 13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes 20 kept in Hi-Z (tristate) after the start of a write access. 27 NAND flash in response to SMWAITn. Zero means 1 cycle, [all …]
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D | oxnas-nand.txt | 1 * Oxford Semiconductor OXNAS NAND Controller 3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings. 6 - compatible: "oxsemi,ox820-nand" 7 - reg: Base address and length for NAND mapped memory. 10 - clocks: phandle to the NAND gate clock if needed. 11 - resets: phandle to the NAND reset control if needed. 15 nandc: nand-controller@41000000 { 16 compatible = "oxsemi,ox820-nand"; 20 #address-cells = <1>; 21 #size-cells = <0>; [all …]
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D | amlogic,meson-nand.txt | 1 Amlogic NAND Flash Controller (NFC) for GXBB/GXL/AXG family SoCs 4 the MTD NAND bindings. 7 - compatible : contains one of: 8 - "amlogic,meson-gxl-nfc" 9 - "amlogic,meson-axg-nfc" 10 - clocks : 11 A list of phandle + clock-specifier pairs for the clocks listed 12 in clock-names. 14 - clock-names: Should contain the following: 15 "core" - NFC module gate clock [all …]
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D | ingenic,nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Ingenic SoCs NAND controller devicetree bindings 10 - Paul Cercueil <paul@crapouillou.net> 13 - $ref: nand-controller.yaml# 18 - ingenic,jz4740-nand 19 - ingenic,jz4725b-nand 20 - ingenic,jz4780-nand [all …]
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/Linux-v5.10/Documentation/devicetree/bindings/gpio/ |
D | ni,169445-nand-gpio.txt | 1 Bindings for the National Instruments 169445 GPIO NAND controller 3 The 169445 GPIO NAND controller has two memory mapped GPIO registers, one 5 intended to be used with the GPIO NAND driver. 8 - compatible: should be "ni,169445-nand-gpio" 9 - reg-names: must contain 10 "dat" - data register 11 - reg: address + size pairs describing the GPIO register sets; 12 order must correspond with the order of entries in reg-names 13 - #gpio-cells: must be set to 2. The first cell is the pin number and 17 - gpio-controller: Marks the device node as a gpio controller. [all …]
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/Linux-v5.10/drivers/mtd/nand/raw/atmel/ |
D | nand-controller.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 13 * Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8) 23 * Derived from Das U-Boot source code 24 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c) 30 * Add Nand Flash Controller support for SAMA5 SoC 38 * - atmel_nand_: all generic structures/functions 39 * - atmel_smc_nand_: all structures/functions specific to the SMC interface 41 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface 43 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block [all …]
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/Linux-v5.10/drivers/mtd/nand/raw/ingenic/ |
D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Ingenic JZ47xx NAND driver 24 #include <linux/jz4780-nemc.h> 28 #define DRV_NAME "ingenic-nand" 46 struct nand_controller controller; member 68 return container_of(ctrl, struct ingenic_nfc, controller); in to_ingenic_nfc() 75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() 77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc() 78 return -ERANGE; in qi_lb60_ooblayout_ecc() 80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc() [all …]
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