1 // SPDX-License-Identifier: GPL-2.0-only
9  *   This is a device driver for the NAND flash controller found on
11  *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
12  *   where 0-3 reflects the chip select for NAND.
34 /* NAND Timing MSRs */
35 #define MSR_NANDF_DATA		0x5140001b	/* NAND Flash Data Timing MSR */
36 #define MSR_NANDF_CTL		0x5140001c	/* NAND Flash Control Timing */
39 /* NAND BAR MSRs */
46 #define FLSH_NOR_NAND		(1ULL<<33)	/* 1 for NAND */
55 /* Registers within the NAND flash controller BAR -- memory mapped */
57 #define MM_NAND_CTL		0x800	/* Any even address 0x800-0x80e */
58 #define MM_NAND_IO		0x801	/* Any odd address 0x801-0x80f */
66 /* Registers within the NAND flash controller BAR -- I/O mapped */
77 #define CS_NAND_CTL_DIST_EN	(1<<4)	/* Enable NAND Distract interrupt */
99 to_cs553x(struct nand_controller *controller)  in to_cs553x()  argument
101 	return container_of(controller, struct cs553x_nand_controller, base);  in to_cs553x()
110 	writeb(ctl, cs553x->mmio + MM_NAND_CTL);  in cs553x_write_ctrl_byte()
111 	writeb(data, cs553x->mmio + MM_NAND_IO);  in cs553x_write_ctrl_byte()
112 	ret = readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,  in cs553x_write_ctrl_byte()
124 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_in()
126 		memcpy_fromio(buf, cs553x->mmio, 0x800);  in cs553x_data_in()
128 		len -= 0x800;  in cs553x_data_in()
130 	memcpy_fromio(buf, cs553x->mmio, len);  in cs553x_data_in()
136 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_data_out()
138 		memcpy_toio(cs553x->mmio, buf, 0x800);  in cs553x_data_out()
140 		len -= 0x800;  in cs553x_data_out()
142 	memcpy_toio(cs553x->mmio, buf, len);  in cs553x_data_out()
151 	return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,  in cs553x_wait_ready()
162 	switch (instr->type) {  in cs553x_exec_instr()
165 					     instr->ctx.cmd.opcode);  in cs553x_exec_instr()
169 		for (i = 0; i < instr->ctx.addr.naddrs; i++) {  in cs553x_exec_instr()
171 						     instr->ctx.addr.addrs[i]);  in cs553x_exec_instr()
178 		cs553x_data_in(cs553x, instr->ctx.data.buf.in,  in cs553x_exec_instr()
179 			       instr->ctx.data.len);  in cs553x_exec_instr()
183 		cs553x_data_out(cs553x, instr->ctx.data.buf.out,  in cs553x_exec_instr()
184 				instr->ctx.data.len);  in cs553x_exec_instr()
188 		ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);  in cs553x_exec_instr()
192 	if (instr->delay_ns)  in cs553x_exec_instr()
193 		ndelay(instr->delay_ns);  in cs553x_exec_instr()
202 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs553x_exec_op()
209 	/* De-assert the CE pin */  in cs553x_exec_op()
210 	writeb(0, cs553x->mmio + MM_NAND_CTL);  in cs553x_exec_op()
211 	for (i = 0; i < op->ninstrs; i++) {  in cs553x_exec_op()
212 		ret = cs553x_exec_instr(cs553x, &op->instrs[i]);  in cs553x_exec_op()
217 	/* Re-assert the CE pin. */  in cs553x_exec_op()
218 	writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);  in cs553x_exec_op()
225 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs_enable_hwecc()
227 	writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);  in cs_enable_hwecc()
233 	struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);  in cs_calculate_ecc()
236 	ecc = readl(cs553x->mmio + MM_NAND_STS);  in cs_calculate_ecc()
248 	if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)  in cs553x_attach_chip()
251 	chip->ecc.size = 256;  in cs553x_attach_chip()
252 	chip->ecc.bytes = 3;  in cs553x_attach_chip()
253 	chip->ecc.hwctl  = cs_enable_hwecc;  in cs553x_attach_chip()
254 	chip->ecc.calculate = cs_calculate_ecc;  in cs553x_attach_chip()
255 	chip->ecc.correct  = nand_correct_data;  in cs553x_attach_chip()
256 	chip->ecc.strength = 1;  in cs553x_attach_chip()
268 	struct cs553x_nand_controller *controller;  in cs553x_init_one()  local
273 	pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",  in cs553x_init_one()
277 		pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");  in cs553x_init_one()
278 		return -ENXIO;  in cs553x_init_one()
282 	controller = kzalloc(sizeof(*controller), GFP_KERNEL);  in cs553x_init_one()
283 	if (!controller) {  in cs553x_init_one()
284 		err = -ENOMEM;  in cs553x_init_one()
288 	this = &controller->chip;  in cs553x_init_one()
289 	nand_controller_init(&controller->base);  in cs553x_init_one()
290 	controller->base.ops = &cs553x_nand_controller_ops;  in cs553x_init_one()
291 	this->controller = &controller->base;  in cs553x_init_one()
295 	new_mtd->owner = THIS_MODULE;  in cs553x_init_one()
298 	controller->mmio = ioremap(adr, 4096);  in cs553x_init_one()
299 	if (!controller->mmio) {  in cs553x_init_one()
300 		pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);  in cs553x_init_one()
301 		err = -EIO;  in cs553x_init_one()
306 	this->bbt_options = NAND_BBT_USE_FLASH;  in cs553x_init_one()
308 	new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);  in cs553x_init_one()
309 	if (!new_mtd->name) {  in cs553x_init_one()
310 		err = -ENOMEM;  in cs553x_init_one()
319 	controllers[cs] = controller;  in cs553x_init_one()
323 	kfree(new_mtd->name);  in cs553x_init_one()
325 	iounmap(controller->mmio);  in cs553x_init_one()
327 	kfree(controller);  in cs553x_init_one()
351 	int err = -ENXIO;  in cs553x_init()
357 		return -ENXIO;  in cs553x_init()
363 		return -ENXIO;  in cs553x_init()
365 	/* If it doesn't have the NAND controller enabled, abort */  in cs553x_init()
368 		pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");  in cs553x_init()
369 		return -ENXIO;  in cs553x_init()
384 			mtd_device_register(nand_to_mtd(&controllers[i]->chip),  in cs553x_init()
400 		struct cs553x_nand_controller *controller = controllers[i];  in cs553x_cleanup()  local
401 		struct nand_chip *this = &controller->chip;  in cs553x_cleanup()
412 		kfree(mtd->name);  in cs553x_cleanup()
416 		iounmap(controller->mmio);  in cs553x_cleanup()
419 		kfree(controller);  in cs553x_cleanup()
427 MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");