| /Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | fsl,ls-scfg-msi.txt | 1 * Freescale Layerscape SCFG PCIe MSI controller
5 - compatible: should be "fsl,<soc-name>-msi" to identify
6 Layerscape PCIe MSI controller block such as:
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
13 - reg: physical base address of the controller and length of memory mapped.
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| D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
14 - The doorbell (the MMIO address written to).
17 they can address. An MSI controller may feature a number of doorbells.
19 - The payload (the value written to the doorbell).
22 MSI controllers may have restrictions on permitted payloads.
24 - Sideband information accompanying the write.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| D | loongson,pch-msi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
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| D | hisilicon,mbigen-v2.txt | 6 MBI is kind of msi interrupt only used on Non-PCI devices.
12 Non-pci devices can connect to mbigen and generate the
18 -------------------------------------------
19 - compatible: Should be "hisilicon,mbigen-v2"
21 - reg: Specifies the base physical address and size of the Mbigen
25 ------------------------------------------
26 - interrupt controller: Identifies the node as an interrupt controller
28 - msi-parent: Specifies the MSI controller this mbigen use.
29 For more detail information,please refer to the generic msi-parent binding in
30 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
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| D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
28 - #interrupt-cells: Specifies the number of cells needed to encode an
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| /Linux-v5.10/Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.txt | 4 - compatible:
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
13 PAXB-based root complex is used for external endpoint devices. PAXC-based
15 - reg: base address and length of the PCIe controller I/O register space
16 - #interrupt-cells: set to <1>
17 - interrupt-map-mask and interrupt-map, standard PCI properties to define the
19 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
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| D | altera-pcie-msi.txt | 1 * Altera PCIe MSI controller
4 - compatible: should contain "altr,msi-1.0"
5 - reg: specifies the physical base address of the controller and
7 - reg-names: must include the following entries:
10 - interrupts: specifies the interrupt source of the parent interrupt
12 parent interrupt controller.
13 - num-vectors: number of vectors, range 1 to 32.
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
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| D | xilinx-nwl-pcie.txt | 4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
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| /Linux-v5.10/drivers/of/ |
| D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Copyright (C) 1996-2001 Cort Dougan
29 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space
48 * of_irq_find_parent - Given a device node, find its interrupt parent node
51 * Returns a pointer to the interrupt parent node, or NULL if the interrupt
52 * parent could not be determined.
57 phandle parent; in of_irq_find_parent() local
63 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent()
69 p = of_find_node_by_phandle(parent); in of_irq_find_parent()
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| /Linux-v5.10/drivers/irqchip/ |
| D | irq-loongson-pch-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
39 .name = "PCH PCI MSI",
50 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
52 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
55 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
56 return -ENOSPC; in pch_msi_allocate_hwirq()
59 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
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| D | irq-gic-v3-its-platform-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
9 #include <linux/msi.h>
14 .name = "ITS-pMSI",
22 /* Suck the DeviceID out of the msi-parent property */ in of_pmsi_get_dev_id()
26 ret = of_parse_phandle_with_args(dev->of_node, in of_pmsi_get_dev_id()
27 "msi-parent", "#msi-cells", in of_pmsi_get_dev_id()
31 return -EINVAL; in of_pmsi_get_dev_id()
43 return -1; in iort_pmsi_get_dev_id()
53 msi_info = msi_get_domain_info(domain->parent); in its_pmsi_prepare()
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| D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
16 #include <linux/dma-iommu.h>
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
31 * [25:16] lowest SPI assigned to MSI
33 * [9:0] Numer of SPIs assigned to MSI
49 /* APM X-Gene with GICv2m MSI_IIDR register value */
70 unsigned long *bm; /* MSI vector bitmap */
87 .name = "MSI",
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| D | irq-gic-v3-its-pci-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2015 ARM Limited, All Rights Reserved.
9 #include <linux/msi.h>
27 .name = "ITS-MSI",
36 int msi, msix, *count = data; in its_pci_msi_vec_count() local
38 msi = max(pci_msi_vec_count(pdev), 0); in its_pci_msi_vec_count()
40 *count += max(msi, msix); in its_pci_msi_vec_count()
62 return -EINVAL; in its_pci_msi_prepare()
64 msi_info = msi_get_domain_info(domain->parent); in its_pci_msi_prepare()
72 if (alias_dev != pdev && alias_dev->subordinate) in its_pci_msi_prepare()
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| D | irq-ls-scfg-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
12 #include <linux/msi.h>
21 #include <linux/dma-iommu.h>
48 struct irq_domain *parent; member
60 .name = "MSI",
76 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
89 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
90 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
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| /Linux-v5.10/arch/x86/kernel/apic/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support of MSI, HPET and DMAR interrupts.
16 #include <linux/msi.h>
28 msg->address_hi = MSI_ADDR_BASE_HI; in __irq_msi_compose_msg()
31 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); in __irq_msi_compose_msg()
33 msg->address_lo = in __irq_msi_compose_msg()
35 ((apic->irq_dest_mode == 0) ? in __irq_msi_compose_msg()
39 MSI_ADDR_DEST_ID(cfg->dest_apicid); in __irq_msi_compose_msg()
41 msg->data = in __irq_msi_compose_msg()
45 MSI_DATA_VECTOR(cfg->vector); in __irq_msi_compose_msg()
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| /Linux-v5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap810-ap0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
14 compatible = "marvell,armada-ap810";
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "arm,psci-0.2";
28 ap810-ap0 {
29 #address-cells = <2>;
30 #size-cells = <2>;
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| D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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| /Linux-v5.10/drivers/base/ |
| D | platform-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MSI framework for platform devices
13 #include <linux/msi.h>
17 #define MAX_DEV_MSIS (1 << (32 - DEV_ID_SHIFT))
21 * and the callback to write the MSI message.
36 * Convert an msi_desc to a globaly unique identifier (per-device
43 devid = desc->platform.msi_priv_data->devid; in platform_msi_calc_hwirq()
45 return (devid << (32 - DEV_ID_SHIFT)) | desc->platform.msi_index; in platform_msi_calc_hwirq()
50 arg->desc = desc; in platform_msi_set_desc()
51 arg->hwirq = platform_msi_calc_hwirq(desc); in platform_msi_set_desc()
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| /Linux-v5.10/drivers/bus/fsl-mc/ |
| D | fsl-mc-msi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Freescale Management Complex (MC) bus driver MSI support
5 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
15 #include <linux/msi.h>
18 #include "fsl-mc-private.h"
22 * Generate a unique ID identifying the interrupt (only used within the MSI
32 return (irq_hw_number_t)(desc->fsl_mc.msi_index + (dev->icid * 10000)); in fsl_mc_domain_calc_hwirq()
38 arg->desc = desc; in fsl_mc_msi_set_desc()
39 arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev), in fsl_mc_msi_set_desc()
48 struct msi_domain_ops *ops = info->ops; in fsl_mc_msi_update_dom_ops()
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| /Linux-v5.10/arch/arm64/boot/dts/broadcom/northstar2/ |
| D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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| /Linux-v5.10/kernel/irq/ |
| D | msi.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/msi.h>
21 * alloc_msi_entry - Allocate an initialize msi_entry
38 INIT_LIST_HEAD(&desc->list); in alloc_msi_entry()
39 desc->dev = dev; in alloc_msi_entry()
40 desc->nvec_used = nvec; in alloc_msi_entry()
42 desc->affinity = kmemdup(affinity, in alloc_msi_entry()
43 nvec * sizeof(*desc->affinity), GFP_KERNEL); in alloc_msi_entry()
44 if (!desc->affinity) { in alloc_msi_entry()
55 kfree(entry->affinity); in free_msi_entry()
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| /Linux-v5.10/arch/mips/boot/dts/loongson/ |
| D | loongson64c_4core_ls7a.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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| D | loongson64g_4core_ls7a.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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| /Linux-v5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 1 * Freescale MSI interrupt controller
4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
17 region must be added because different MSI group has different MSIIR1 offset.
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
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