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/Linux-v5.10/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Loongson PCH MSI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
26 u32 value of the base of parent HyperTransport vector allocated
[all …]
/Linux-v5.10/drivers/irqchip/
Dirq-loongson-pch-msi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Loongson PCH MSI support
7 #define pr_fmt(fmt) "pch-msi: " fmt
10 #include <linux/msi.h>
39 .name = "PCH PCI MSI",
50 mutex_lock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
52 first = bitmap_find_free_region(priv->msi_map, priv->num_irqs, in pch_msi_allocate_hwirq()
55 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
56 return -ENOSPC; in pch_msi_allocate_hwirq()
59 mutex_unlock(&priv->msi_map_lock); in pch_msi_allocate_hwirq()
[all …]
/Linux-v5.10/arch/mips/boot/dts/loongson/
Dloongson64c_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64c-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64c-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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Dloongson64g_4core_ls7a.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "loongson64g-package.dtsi"
6 #include "ls7a-pch.dtsi"
9 compatible = "loongson,loongson64g-4core-ls7a";
13 htvec: interrupt-controller@efdfb000080 {
14 compatible = "loongson,htvec-1.0";
16 interrupt-controller;
17 #interrupt-cells = <1>;
19 interrupt-parent = <&liointc>;
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Dls7a-pch.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
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/Linux-v5.10/drivers/crypto/cavium/nitrox/
Dnitrox_isr.c1 // SPDX-License-Identifier: GPL-2.0
14 * - NPS packet ring, AQMQ ring and ZQMQ ring
18 /* base entry for packet ring/port */
23 * nps_pkt_slc_isr - IRQ handler for NPS solicit port
31 struct nitrox_cmdq *cmdq = qvec->cmdq; in nps_pkt_slc_isr()
33 slc_cnts.value = readq(cmdq->compl_cnt_csr_addr); in nps_pkt_slc_isr()
36 tasklet_hi_schedule(&qvec->resp_tasklet); in nps_pkt_slc_isr()
206 struct nitrox_device *ndev = qvec->ndev; in nps_core_int_tasklet()
209 if (ndev->mode == __NDEV_MODE_PF) { in nps_core_int_tasklet()
219 * nps_core_int_isr - interrupt handler for NITROX errors and
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb4vf/
Dcxgb4vf_main.c2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
42 #include <linux/dma-mapping.h>
74 * order MSI-X then MSI. This parameter determines which of these schemes the
77 * msi = 2: choose from among MSI-X and MSI
78 * msi = 1: only consider MSI interrupts
82 * the PCI-E SR-IOV standard).
88 static int msi = MSI_DEFAULT; variable
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Dadapter.h2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
61 * MSI-X interrupt index usage.
63 MSIX_FW = 0, /* MSI-X index for firmware Q */
64 MSIX_IQFLINT = 1, /* MSI-X index base for Ingress Qs */
89 * Per-"port" information. This is really per-Virtual Interface information
117 * absolute Queue ID base of the section of the Queue ID space allocated to
122 * SGE free-list queue state.
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/Linux-v5.10/arch/powerpc/platforms/4xx/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Adding PCI-E MSI support for PPC4XX SoCs.
12 #include <linux/msi.h>
19 #include <asm/ppc-pci.h>
21 #include <asm/dcr-regs.h>
51 err = msi_bitmap_alloc(&msi_data->bitmap, msi_irqs, in ppc4xx_msi_init_allocator()
52 dev->dev.of_node); in ppc4xx_msi_init_allocator()
56 err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
58 msi_bitmap_free(&msi_data->bitmap); in ppc4xx_msi_init_allocator()
67 int int_no = -ENOMEM; in ppc4xx_setup_msi_irqs()
[all …]
/Linux-v5.10/drivers/i2c/busses/
Di2c-ismt.c65 #include <linux/dma-mapping.h>
70 #include <linux/io-64-nonatomic-lo-hi.h>
86 /* Hardware Descriptor Constants - Control Field */
95 /* Hardware Descriptor Constants - Status Field */
116 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
152 /* MSI Control Register (MSICTL) bit definitions */
153 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
173 struct ismt_desc *hw; /* descriptor virt base addr */
174 dma_addr_t io_rng_dma; /* descriptor HW base addr */
192 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
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/Linux-v5.10/drivers/ntb/hw/amd/
Dntb_hw_amd.c8 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
17 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
65 #define NTB_DESC "AMD(R) PCI-E Non-Transparent Bridge Driver"
78 if (idx < 0 || idx > ndev->mw_count) in ndev_mw_to_bar()
79 return -EINVAL; in ndev_mw_to_bar()
81 return ndev->dev_data->mw_idx << idx; in ndev_mw_to_bar()
87 return -EINVAL; in amd_ntb_mw_count()
89 return ntb_ndev(ntb)->mw_count; in amd_ntb_mw_count()
101 return -EINVAL; in amd_ntb_mw_get_align()
114 *size_max = pci_resource_len(ndev->ntb.pdev, bar); in amd_ntb_mw_get_align()
[all …]
/Linux-v5.10/arch/ia64/kernel/
Dirq_ia64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 1998-2001 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
54 /* default base addr of IPI table */
61 * Legacy IRQ to IA-64 vector translation table.
73 [0 ... NR_IRQS - 1] = {
80 [0 ... IA64_NUM_VECTORS - 1] = -1
84 [0 ... IA64_NUM_VECTORS - 1] = CPU_MASK_NONE
88 [0 ... NR_IRQS -1] = IRQ_UNUSED
98 return -ENOSPC; in find_unassigned_irq()
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/Linux-v5.10/drivers/ntb/hw/intel/
Dntb_hw_gen1.c9 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
19 * Copyright (C) 2016 T-Platforms. All Rights Reserved.
66 #define NTB_DESC "Intel(R) PCI-E Non-Transparent Bridge Driver"
74 #define bar0_off(base, bar) ((base) + ((bar) << 2)) argument
75 #define bar2_off(base, bar) bar0_off(base, (bar) - 2) argument
88 static int b2b_mw_idx = -1;
105 "XEON B2B USD BAR 2 64-bit address");
110 "XEON B2B USD BAR 4 64-bit address");
115 "XEON B2B USD split-BAR 4 32-bit address");
120 "XEON B2B USD split-BAR 5 32-bit address");
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb3/
Dcxgb3_main.c2 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
38 #include <linux/dma-mapping.h>
77 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
99 CH_DEVICE(0x35, 6), /* T3C20-derived T3C10 */
100 CH_DEVICE(0x36, 3), /* S320E-CR */
101 CH_DEVICE(0x37, 7), /* N320E-G2 */
117 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
120 * msi = 2: choose from among all three options
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/Linux-v5.10/arch/alpha/kernel/
Dsys_marvel.c1 // SPDX-License-Identifier: GPL-2.0
52 * -----+-----+--------+--- in io7_device_interrupt()
57 * 0x0800 - 0x0ff0 - 0x0800 + (LSI id << 4) in io7_device_interrupt()
58 * 0x1000 - 0x2ff0 - 0x1000 + (MSI_DAT<8:0> << 4) in io7_device_interrupt()
61 irq = ((vector & 0xffff) - 0x800) >> 4; in io7_device_interrupt()
81 "%s for nonexistent io7 -- vec %x, pid %d\n", in io7_get_irq_ctl()
87 irq -= 16; /* subtract legacy bias */ in io7_get_irq_ctl()
91 "%s for invalid irq -- pid %d adjusted irq %x\n", in io7_get_irq_ctl()
96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
97 if (irq >= 0x80) /* MSI */ in io7_get_irq_ctl()
[all …]
/Linux-v5.10/arch/powerpc/kernel/
Dprom_init.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1996-2005 Paul Mackerras.
42 #include <asm/asm-prototypes.h>
43 #include <asm/ultravisor-api.h>
68 * On ppc32 we compile with -mrelocatable, which means that references
79 * arguments to call_prom should be 32-bit values.
127 __be64 base; member
218 * Error results ... some OF calls will return "-1" on error, some
224 #define PROM_ERROR (-1u)
238 return c1 < c2 ? -1 : 1; in prom_strcmp()
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/Linux-v5.10/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_main.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
110 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
127 #define FW4_CFNAME "cxgb4/t4-config.txt"
128 #define FW5_CFNAME "cxgb4/t5-config.txt"
129 #define FW6_CFNAME "cxgb4/t6-config.txt"
145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
148 * msi = 2: choose from among all three options
149 * msi = 1: only consider MSI and INTx interrupts
[all …]
Dcxgb4.h4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
61 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
138 FEC_RS = 1 << 1, /* Reed-Solomon */
139 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
262 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
263 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
264 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
265 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
[all …]
Dt4_hw.c4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
43 * t4_wait_op_done_val - wait until an operation is completed
46 * @mask: a single-bit field within @reg that indicates completion
55 * operation completes and -EAGAIN otherwise.
68 if (--attempts == 0) in t4_wait_op_done_val()
69 return -EAGAIN; in t4_wait_op_done_val()
83 * t4_set_reg_field - set a register field to a value
102 * t4_read_indirect - read indirectly addressed registers
[all …]
/Linux-v5.10/drivers/net/wireless/intel/iwlwifi/pcie/
Dinternal.h8 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
31 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
33 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
34 * Copyright(c) 2018 - 2019 Intel Corporation
75 #include "iwl-fh.h"
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/Linux-v5.10/drivers/net/ethernet/marvell/octeontx2/af/
Drvu.c1 // SPDX-License-Identifier: GPL-2.0
25 #define DRV_NAME "octeontx2-af"
62 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
64 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1; in rvu_setup_hw_capabilities()
65 hw->cap.nix_fixed_txschq_mapping = false; in rvu_setup_hw_capabilities()
66 hw->cap.nix_shaping = true; in rvu_setup_hw_capabilities()
67 hw->cap.nix_tx_link_bp = true; in rvu_setup_hw_capabilities()
68 hw->cap.nix_rx_multicast = true; in rvu_setup_hw_capabilities()
71 hw->cap.nix_fixed_txschq_mapping = true; in rvu_setup_hw_capabilities()
72 hw->cap.nix_txsch_per_cgx_lmac = 4; in rvu_setup_hw_capabilities()
[all …]
/Linux-v5.10/drivers/net/ethernet/netronome/nfp/
Dnfp_net.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
20 #include <linux/io-64-nonatomic-hi-lo.h>
31 if (__nn->dp.netdev) \
32 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \
34 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \
47 if (__dp->netdev) \
48 netdev_warn(__dp->netdev, fmt, ## args); \
50 dev_warn(__dp->dev, fmt, ## args); \
113 #define D_IDX(ring, idx) ((idx) & ((ring)->cnt - 1))
[all …]
/Linux-v5.10/include/linux/
Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
53 * The PCI interface treats multi-function devices as independent
61 * In the interest of not exposing interfaces to user-space unnecessarily,
62 * the following kernel-only defines are being added here.
73 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
79 return kobject_name(&slot->kobj); in pci_slot_name()
90 /* #0-5: standard PCI resources */
92 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
97 /* Device-specific resources */
[all …]
/Linux-v5.10/drivers/net/ethernet/intel/i40e/
Di40e_main.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
27 static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation.";
51 /* i40e_pci_tbl - PCI Device ID Table
89 static int debug = -1;
93 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
100 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
109 struct i40e_pf *pf = (struct i40e_pf *)hw->back; in i40e_allocate_dma_mem_d()
111 mem->size = ALIGN(size, alignment); in i40e_allocate_dma_mem_d()
112 mem->va = dma_alloc_coherent(&pf->pdev->dev, mem->size, &mem->pa, in i40e_allocate_dma_mem_d()
[all …]
/Linux-v5.10/drivers/scsi/csiostor/
Dcsio_hw.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
56 /* Default MSI param level */
64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
[all …]

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