Lines Matching +full:msi +full:- +full:base +full:- +full:vec
2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
17 * - Redistributions of source code must retain the above
21 * - Redistributions in binary form must reproduce the above
61 * MSI-X interrupt index usage.
63 MSIX_FW = 0, /* MSI-X index for firmware Q */
64 MSIX_IQFLINT = 1, /* MSI-X index base for Ingress Qs */
89 * Per-"port" information. This is really per-Virtual Interface information
117 * absolute Queue ID base of the section of the Queue ID space allocated to
122 * SGE free-list queue state.
135 * Write-once/infrequently fields.
136 * -------------------------------
176 * Write-once/infrequently fields.
177 * -------------------------------
233 unsigned int in_use; /* # of in-use TX descriptors */
241 * Write-once/infrequently fields.
242 * -------------------------------
279 * forwarded interrupts (when in MSI mode).
287 * State for managing "starving Free Lists" -- Free Lists which have
302 * Write-once/infrequently fields.
303 * -------------------------------
323 * [potentially large] Base Queue ID. We perform the reverse map by
325 * subtracting off the Base Queue ID and then use a Relative Queue ID
336 * Utility macros to convert Absolute- to Relative-Queue indices and Egress-
337 * and Ingress-Queues. The EQ_MAP() and IQ_MAP() macros which provide
338 * pointers to Ingress- and Egress-Queues can be used as both L- and R-values
340 #define EQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->egr_base))
341 #define IQ_IDX(s, abs_id) ((unsigned int)((abs_id) - (s)->ingr_base))
343 #define EQ_MAP(s, abs_id) ((s)->egr_map[EQ_IDX(s, abs_id)])
344 #define IQ_MAP(s, abs_id) ((s)->ingr_map[IQ_IDX(s, abs_id)])
350 for (iter = 0; iter < (sge)->ethqsets; iter++)
363 * Per-"adapter" (Virtual Function) information.
380 unsigned short vec; member
423 * t4_read_reg - read a HW register
427 * Returns the 32-bit value of the given HW register.
431 return readl(adapter->regs + reg_addr); in t4_read_reg()
435 * t4_write_reg - write a HW register
440 * Write a 32-bit value into the given HW register.
444 writel(val, adapter->regs + reg_addr); in t4_write_reg()
461 * t4_read_reg64 - read a 64-bit HW register
465 * Returns the 64-bit value of the given HW register.
469 return readq(adapter->regs + reg_addr); in t4_read_reg64()
473 * t4_write_reg64 - write a 64-bit HW register
478 * Write a 64-bit value into the given HW register.
483 writeq(val, adapter->regs + reg_addr); in t4_write_reg64()
487 * port_name - return the string name of a port
495 return adapter->port[pidx]->name; in port_name()
499 * t4_os_set_hw_addr - store a port's MAC address in SW
510 memcpy(adapter->port[pidx]->dev_addr, hw_addr, ETH_ALEN); in t4_os_set_hw_addr()
514 * netdev2pinfo - return the port_info structure associated with a net_device
525 * adap2pinfo - return the port_info of a port
533 return netdev_priv(adapter->port[pidx]); in adap2pinfo()
537 * netdev2adap - return the adapter structure associated with a net_device
544 return netdev2pinfo(dev)->adapter; in netdev2adap()