| /Linux-v5.15/drivers/memory/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Memory devices
6 menuconfig MEMORY config
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
15 if MEMORY
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
31 controller, say Y or M here.
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| /Linux-v5.15/drivers/memory/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
20 This driver is for the External Memory Controller (EMC) found on
22 This driver is required to change memory timings / clock rate for
23 external memory.
26 tristate "NVIDIA Tegra30 External Memory Controller driver"
31 This driver is for the External Memory Controller (EMC) found on
33 This driver is required to change memory timings / clock rate for
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | ddr.txt | 1 Freescale DDR memory controller
5 - compatible : Should include "fsl,chip-memory-controller" where
7 "fsl,qoriq-memory-controller".
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
10 - little-endian : Specifies little-endian access to registers
11 If omitted, big-endian will be used.
15 memory-controller@2000 {
16 compatible = "fsl,bsc9132-memory-controller";
24 ddr1: memory-controller@8000 {
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| /Linux-v5.15/drivers/edac/ |
| D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
59 Not all machines support hardware-driven error report. Some of those
60 provide a BIOS-driven error report mechanism via ACPI, using the
64 When this option is enabled, it will disable the hardware-driven
[all …]
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| D | ppc4xx_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
27 * As realized in the 405EX[r], this controller features:
29 * - Support for registered- and non-registered DDR1 and DDR2 memory.
30 * - 32-bit or 16-bit memory interface with optional ECC.
34 * - 4-bit SEC/DED
35 * - Aligned-nibble error detect
36 * - Bypass mode
38 * - Two (2) memory banks/ranks.
39 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
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| D | mpc85xx_edac.c | 2 * Freescale MPC85xx Memory Controller kernel module
8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
51 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; in mpc85xx_pci_check()
54 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); in mpc85xx_pci_check()
58 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); in mpc85xx_pci_check()
66 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); in mpc85xx_pci_check()
68 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
70 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); in mpc85xx_pci_check()
72 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
74 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
[all …]
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| /Linux-v5.15/drivers/char/agp/ |
| D | frontend.c | 4 * Copyright (C) 2002-2003 Dave Jones
53 curr = agp_fe.current_controller->pool; in agp_find_mem_by_key()
56 if (curr->key == key) in agp_find_mem_by_key()
58 curr = curr->next; in agp_find_mem_by_key()
61 DBG("key=%d -> mem=%p", key, curr); in agp_find_mem_by_key()
70 /* Check to see if this is even in the memory pool */ in agp_remove_from_pool()
73 if (agp_find_mem_by_key(temp->key) != NULL) { in agp_remove_from_pool()
74 next = temp->next; in agp_remove_from_pool()
75 prev = temp->prev; in agp_remove_from_pool()
78 prev->next = next; in agp_remove_from_pool()
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
[all …]
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| D | arm,pl353-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
14 The PL353 Static Memory Controller is a bus where you can connect two kinds
15 of memory interfaces, which are NAND and memory mapped interfaces (such as
23 const: arm,pl353-smc-r2p1
[all …]
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| D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
[all …]
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| D | nvidia,tegra20-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
[all …]
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| /Linux-v5.15/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 used to offload memory copies in the network stack and
65 Enable support for Altera / Intel mSGDMA controller.
93 Support the Atmel AHB DMA controller.
100 Support the Atmel XDMA controller.
103 tristate "Analog Devices AXI-DMAC DMA support"
109 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
110 controller is often used in Analog Devices' reference designs for FPGA
140 This selects support for the DMA controller in Ingenic JZ4780 SoCs.
142 devices which can use the DMA controller, say Y or M here.
[all …]
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| /Linux-v5.15/Documentation/admin-guide/cgroup-v1/ |
| D | memory.rst | 2 Memory Resource Controller
12 The Memory Resource Controller has generically been referred to as the
13 memory controller in this document. Do not confuse memory controller
14 used here with the memory controller that is used in hardware.
17 When we mention a cgroup (cgroupfs's directory) with memory controller,
18 we call it "memory cgroup". When you see git-log and source code, you'll
22 Benefits and Purpose of the memory controller
25 The memory controller isolates the memory behaviour of a group of tasks
27 uses of the memory controller. The memory controller can be used to
30 Memory-hungry applications can be isolated and limited to a smaller
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra20-host1x.txt | 4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/ata/ |
| D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
12 core memory resource.
13 Third memory resource shall be the host controller
14 diagnostic memory resource.
[all …]
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| /Linux-v5.15/Documentation/admin-guide/ |
| D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
12 of cgroup including core and specific controller behaviors. All
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
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| /Linux-v5.15/Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
23 "BriefDescription": "Memory controller clock ticks",
40 "BriefDescription": "Cycles Memory is in self refresh power mode",
50 "BriefDescription": "Pre-charges due to page misses",
59 "BriefDescription": "Pre-charge for reads",
73 …te commands sent on this channel due to a write request to the iMC (Memory Controller). Activate …
83 …on": "Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS comm…
108 … "DRAM CAS (Column Address Strobe) Commands.; DRAM WR_CAS (w/ and w/out auto-pre) in Write Major M…
113 …nts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode.",
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/mips/brcm/ |
| D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/mtd/ |
| D | aspeed-smc.txt | 1 * Aspeed Firmware Memory controller
2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
8 The two SPI flash memory controllers in the AST2500 each support two
12 - compatible : Should be one of
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
18 - reg : the first contains the control register location and length,
[all …]
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| /Linux-v5.15/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-memory.json | 3 "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
13 "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
23 "BriefDescription": "Memory controller clock ticks",
40 "BriefDescription": "Cycles Memory is in self refresh power mode",
50 "BriefDescription": "Pre-charges due to page misses",
59 "BriefDescription": "Pre-charge for reads",
68 …": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
76 …": "Write requests allocated in the PMM Write Pending Queue for Intel Optane DC persistent memory",
84 …"BriefDescription": "Intel Optane DC persistent memory bandwidth read (MB/sec). Derived from unc_m…
89 "ScaleUnit": "6.103515625E-5MB/sec",
[all …]
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| /Linux-v5.15/Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
16 * Memory devices
18 The individual DRAM chips on a memory stick. These devices commonly
20 provides the number of bits that the memory controller expects:
23 * Memory Stick
25 A printed circuit board that aggregates multiple memory devices in
28 called DIMM (Dual Inline Memory Module).
30 * Memory Socket
32 A physical connector on the motherboard that accepts a single memory
[all …]
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| /Linux-v5.15/Documentation/devicetree/bindings/mfd/ |
| D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
11 The LPC controller is represented as a multi-function device to account for the
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
[all …]
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| /Linux-v5.15/drivers/memory/samsung/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
5 Support for the Memory Controller (MC) devices found on
11 tristate "Exynos5422 Dynamic Memory Controller driver"
17 This adds driver for Exynos5422 DMC (Dynamic Memory Controller).
20 different frequency. The timings are calculated based on DT memory
24 bool "Exynos SROM controller driver" if COMPILE_TEST
27 This adds driver for Samsung Exynos SoC SROM controller. The driver
30 is provided, the driver enables support for external memory
|
| /Linux-v5.15/drivers/mmc/host/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # MMC/SD host controller drivers
6 comment "MMC/SD/SDIO Host Controller Drivers"
28 bool "Qualcomm Data Mover for SD Card Controller"
32 This selects the Qualcomm Data Mover lite/local on SD Card controller.
39 bool "STMicroelectronics STM32 SDMMC Controller"
43 This selects the STMicroelectronics STM32 SDMMC host controller.
59 tristate "Secure Digital Host Controller Interface support"
62 This selects the generic Secure Digital Host Controller Interface.
66 If you have a controller with this interface, say Y or M here. You
[all …]
|
