Lines Matching +full:memory +full:- +full:controller
4 - compatible: "nvidia,tegra<chip>-host1x"
5 - reg: Physical base address and length of the controller's registers.
6 For pre-Tegra186, one entry describing the whole register area.
7 For Tegra186, one entry for each entry in reg-names:
8 "vm" - VM region assigned to Linux
9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor)
10 - interrupts: The interrupt outputs from the controller.
11 - #address-cells: The number of cells used to represent physical base addresses
13 - #size-cells: The number of cells used to represent the size of an address
15 - ranges: The mapping of the host1x address space to the CPU address space.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
20 - reset-names: Must include the following entries:
21 - host1x
23 Each host1x client module having to perform DMA through the Memory Controller
24 should have the interconnect endpoints set to the Memory Client and External
25 Memory respectively.
27 The host1x top-level node defines a number of children, each representing one
30 - mpe: video encoder
33 - compatible: "nvidia,tegra<chip>-mpe"
34 - reg: Physical base address and length of the controller's registers.
35 - interrupts: The interrupt outputs from the controller.
36 - clocks: Must contain one entry, for the module clock.
37 See ../clocks/clock-bindings.txt for details.
38 - resets: Must contain an entry for each entry in reset-names.
40 - reset-names: Must include the following entries:
41 - mpe
44 - interconnects: Must contain entry for the MPE memory clients.
45 - interconnect-names: Must include name of the interconnect path for each
47 available memory clients, see MEMORY CONTROLLER section.
49 - vi: video input
52 - compatible: "nvidia,tegra<chip>-vi"
53 - reg: Physical base address and length of the controller registers.
54 - interrupts: The interrupt outputs from the controller.
55 - clocks: clocks: Must contain one entry, for the module clock.
56 See ../clocks/clock-bindings.txt for details.
57 - Tegra20/Tegra30/Tegra114/Tegra124:
58 - resets: Must contain an entry for each entry in reset-names.
60 - reset-names: Must include the following entries:
61 - vi
62 - Tegra210:
63 - power-domains: Must include venc powergate node as vi is in VE partition.
69 Documentation/devicetree/bindings/media/video-interfaces.txt
75 - csi: mipi csi interface to vi
78 - compatible: "nvidia,tegra210-csi"
79 - reg: Physical base address offset to parent and length of the controller
81 - clocks: Must contain entries csi, cilab, cilcd, cile, csi_tpg clocks.
82 See ../clocks/clock-bindings.txt for details.
83 - power-domains: Must include sor powergate node as csicil is in
91 - reg: csi port number. Valid port numbers are 0 through 5.
92 - nvidia,mipi-calibrate: Should contain a phandle and a specifier
94 calibrated. See also ../display/tegra/nvidia,tegra114-mipi.txt.
102 Documentation/devicetree/bindings/media/video-interfaces.txt
110 - reg: 0
114 - data-lanes: an array of data lane from 1 to 8. Valid array
116 - remote-endpoint: phandle to sensor 'endpoint' node.
120 - reg: 1
124 - remote-endpoint: phandle to vi port 'endpoint' node.
127 - interconnects: Must contain entry for the VI memory clients.
128 - interconnect-names: Must include name of the interconnect path for each
130 available memory clients, see MEMORY CONTROLLER section.
132 - epp: encoder pre-processor
135 - compatible: "nvidia,tegra<chip>-epp"
136 - reg: Physical base address and length of the controller's registers.
137 - interrupts: The interrupt outputs from the controller.
138 - clocks: Must contain one entry, for the module clock.
139 See ../clocks/clock-bindings.txt for details.
140 - resets: Must contain an entry for each entry in reset-names.
142 - reset-names: Must include the following entries:
143 - epp
146 - interconnects: Must contain entry for the EPP memory clients.
147 - interconnect-names: Must include name of the interconnect path for each
149 available memory clients, see MEMORY CONTROLLER section.
151 - isp: image signal processor
154 - compatible: "nvidia,tegra<chip>-isp"
155 - reg: Physical base address and length of the controller's registers.
156 - interrupts: The interrupt outputs from the controller.
157 - clocks: Must contain one entry, for the module clock.
158 See ../clocks/clock-bindings.txt for details.
159 - resets: Must contain an entry for each entry in reset-names.
161 - reset-names: Must include the following entries:
162 - isp
165 - interconnects: Must contain entry for the ISP memory clients.
166 - interconnect-names: Must include name of the interconnect path for each
168 available memory clients, see MEMORY CONTROLLER section.
170 - gr2d: 2D graphics engine
173 - compatible: "nvidia,tegra<chip>-gr2d"
174 - reg: Physical base address and length of the controller's registers.
175 - interrupts: The interrupt outputs from the controller.
176 - clocks: Must contain one entry, for the module clock.
177 See ../clocks/clock-bindings.txt for details.
178 - resets: Must contain an entry for each entry in reset-names.
180 - reset-names: Must include the following entries:
181 - 2d
184 - interconnects: Must contain entry for the GR2D memory clients.
185 - interconnect-names: Must include name of the interconnect path for each
187 available memory clients, see MEMORY CONTROLLER section.
189 - gr3d: 3D graphics engine
192 - compatible: "nvidia,tegra<chip>-gr3d"
193 - reg: Physical base address and length of the controller's registers.
194 - clocks: Must contain an entry for each entry in clock-names.
195 See ../clocks/clock-bindings.txt for details.
196 - clock-names: Must include the following entries:
198 - 3d
200 - 3d2 (Only required on SoCs with two 3D clocks)
201 - resets: Must contain an entry for each entry in reset-names.
203 - reset-names: Must include the following entries:
204 - 3d
205 - 3d2 (Only required on SoCs with two 3D clocks)
208 - interconnects: Must contain entry for the GR3D memory clients.
209 - interconnect-names: Must include name of the interconnect path for each
211 available memory clients, see MEMORY CONTROLLER section.
213 - dc: display controller
216 - compatible: "nvidia,tegra<chip>-dc"
217 - reg: Physical base address and length of the controller's registers.
218 - interrupts: The interrupt outputs from the controller.
219 - clocks: Must contain an entry for each entry in clock-names.
220 See ../clocks/clock-bindings.txt for details.
221 - clock-names: Must include the following entries:
222 - dc
224 - parent
225 - resets: Must contain an entry for each entry in reset-names.
227 - reset-names: Must include the following entries:
228 - dc
229 - nvidia,head: The number of the display controller head. This is used to
233 Each display controller node has a child node, named "rgb", that represents
234 the RGB output associated with the controller. It can take the following
236 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
237 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
238 - nvidia,edid: supplies a binary EDID blob
239 - nvidia,panel: phandle of a display panel
240 - interconnects: Must contain entry for the DC memory clients.
241 - interconnect-names: Must include name of the interconnect path for each
243 available memory clients, see MEMORY CONTROLLER section.
245 - hdmi: High Definition Multimedia Interface
248 - compatible: "nvidia,tegra<chip>-hdmi"
249 - reg: Physical base address and length of the controller's registers.
250 - interrupts: The interrupt outputs from the controller.
251 - hdmi-supply: supply for the +5V HDMI connector pin
252 - vdd-supply: regulator for supply voltage
253 - pll-supply: regulator for PLL
254 - clocks: Must contain an entry for each entry in clock-names.
255 See ../clocks/clock-bindings.txt for details.
256 - clock-names: Must include the following entries:
257 - hdmi
259 - parent
260 - resets: Must contain an entry for each entry in reset-names.
262 - reset-names: Must include the following entries:
263 - hdmi
266 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
267 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
268 - nvidia,edid: supplies a binary EDID blob
269 - nvidia,panel: phandle of a display panel
271 - tvo: TV encoder output
274 - compatible: "nvidia,tegra<chip>-tvo"
275 - reg: Physical base address and length of the controller's registers.
276 - interrupts: The interrupt outputs from the controller.
277 - clocks: Must contain one entry, for the module clock.
278 See ../clocks/clock-bindings.txt for details.
280 - dsi: display serial interface
283 - compatible: "nvidia,tegra<chip>-dsi"
284 - reg: Physical base address and length of the controller's registers.
285 - clocks: Must contain an entry for each entry in clock-names.
286 See ../clocks/clock-bindings.txt for details.
287 - clock-names: Must include the following entries:
288 - dsi
290 - lp
291 - parent
292 - resets: Must contain an entry for each entry in reset-names.
294 - reset-names: Must include the following entries:
295 - dsi
296 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
297 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
299 ../display/tegra/nvidia,tegra114-mipi.txt.
302 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
303 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
304 - nvidia,edid: supplies a binary EDID blob
305 - nvidia,panel: phandle of a display panel
306 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
309 - sor: serial output resource
312 - compatible: Should be:
313 - "nvidia,tegra124-sor": for Tegra124 and Tegra132
314 - "nvidia,tegra132-sor": for Tegra132
315 - "nvidia,tegra210-sor": for Tegra210
316 - "nvidia,tegra210-sor1": for Tegra210
317 - "nvidia,tegra186-sor": for Tegra186
318 - "nvidia,tegra186-sor1": for Tegra186
319 - reg: Physical base address and length of the controller's registers.
320 - interrupts: The interrupt outputs from the controller.
321 - clocks: Must contain an entry for each entry in clock-names.
322 See ../clocks/clock-bindings.txt for details.
323 - clock-names: Must include the following entries:
324 - sor: clock input for the SOR hardware
325 - out: SOR output clock
326 - parent: input for the pixel clock
327 - dp: reference clock for the SOR clock
328 - safe: safe reference for the SOR clock during power up
331 - pad: SOR pad output clock (on Tegra186 and later)
334 - source: source clock for the SOR clock (obsolete, use "out" instead)
336 - resets: Must contain an entry for each entry in reset-names.
338 - reset-names: Must include the following entries:
339 - sor
342 - nvidia,interface: index of the SOR interface
345 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
346 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
347 - nvidia,edid: supplies a binary EDID blob
348 - nvidia,panel: phandle of a display panel
349 - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
354 - nvidia,dpaux: phandle to a DispayPort AUX interface
356 - dpaux: DisplayPort AUX interface
357 - compatible : Should contain one of the following:
358 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132
359 - "nvidia,tegra210-dpaux": for Tegra210
360 - reg: Physical base address and length of the controller's registers.
361 - interrupts: The interrupt outputs from the controller.
362 - clocks: Must contain an entry for each entry in clock-names.
363 See ../clocks/clock-bindings.txt for details.
364 - clock-names: Must include the following entries:
365 - dpaux: clock input for the DPAUX hardware
366 - parent: reference clock
367 - resets: Must contain an entry for each entry in reset-names.
369 - reset-names: Must include the following entries:
370 - dpaux
371 - vdd-supply: phandle of a supply that powers the DisplayPort link
372 - i2c-bus: Subnode where I2C slave devices are listed. This subnode
376 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information
377 regarding the DPAUX pad controller bindings.
379 - vic: Video Image Compositor
380 - compatible : "nvidia,tegra<chip>-vic"
381 - reg: Physical base address and length of the controller's registers.
382 - interrupts: The interrupt outputs from the controller.
383 - clocks: Must contain an entry for each entry in clock-names.
384 See ../clocks/clock-bindings.txt for details.
385 - clock-names: Must include the following entries:
386 - vic: clock input for the VIC hardware
387 - resets: Must contain an entry for each entry in reset-names.
389 - reset-names: Must include the following entries:
390 - vic
393 - interconnects: Must contain entry for the VIC memory clients.
394 - interconnect-names: Must include name of the interconnect path for each
396 available memory clients, see MEMORY CONTROLLER section.
404 compatible = "nvidia,tegra20-host1x", "simple-bus";
410 reset-names = "host1x";
412 #address-cells = <1>;
413 #size-cells = <1>;
418 compatible = "nvidia,tegra20-mpe";
423 reset-names = "mpe";
427 compatible = "nvidia,tegra210-vi";
430 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
431 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
434 power-domains = <&pd_venc>;
436 #address-cells = <1>;
437 #size-cells = <1>;
442 #address-cells = <1>;
443 #size-cells = <0>;
448 remote-endpoint = <&imx219_csi_out0>;
454 compatible = "nvidia,tegra210-csi";
456 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
460 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
463 assigned-clock-rates = <102000000>,
473 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
474 power-domains = <&pd_sor>;
476 #address-cells = <1>;
477 #size-cells = <0>;
481 nvidia,mipi-calibrate = <&mipi 0x001>;
484 #address-cells = <1>;
485 #size-cells = <0>;
490 data-lanes = <1 2>;
491 remote-endpoint = <&imx219_out0>;
498 remote-endpoint = <&imx219_vi_in0>;
507 compatible = "nvidia,tegra20-epp";
512 reset-names = "epp";
516 compatible = "nvidia,tegra20-isp";
521 reset-names = "isp";
525 compatible = "nvidia,tegra20-gr2d";
530 reset-names = "2d";
534 compatible = "nvidia,tegra20-gr3d";
538 reset-names = "3d";
542 compatible = "nvidia,tegra20-dc";
547 clock-names = "dc", "parent";
549 reset-names = "dc";
555 interconnect-names = "wina",
566 compatible = "nvidia,tegra20-dc";
571 clock-names = "dc", "parent";
573 reset-names = "dc";
579 interconnect-names = "wina",
590 compatible = "nvidia,tegra20-hdmi";
595 clock-names = "hdmi", "parent";
597 reset-names = "hdmi";
602 compatible = "nvidia,tegra20-tvo";
610 compatible = "nvidia,tegra20-dsi";
614 clock-names = "dsi", "parent";
616 reset-names = "dsi";