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/Linux-v6.1/Documentation/devicetree/bindings/net/
Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
[all …]
Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
[all …]
Dbrcm,mdio-mux-iproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer found in Broadcom iProc based SoCs.
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs and could accept MDIO transaction compatible to C-22 or
15 C-45 Clause. When child bus is selected, one needs to select these two
16 properties as well to generate desired MDIO transaction on appropriate bus.
[all …]
Dbrcm,bcm6368-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
22 const: brcm,bcm6368-mdio-mux
[all …]
Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller bindings
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
/Linux-v6.1/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
[all …]
Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube")
5 "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or
6 "lantiq,xrx200-pinctrl")
7 "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl")
8 "lantiq,<chip>-pinctrl", where <chip> is:
14 - reg: Should contain the physical address and length of the gpio/pinmux
17 Please refer to pinctrl-bindings.txt in this directory for details of the
24 mux function to select on those group(s), and two pin configuration parameters:
25 pull-up and open-drain
31 other words, a subnode that lists a mux function but no pin configuration
[all …]
/Linux-v6.1/arch/powerpc/boot/dts/fsl/
Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
[all …]
Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
[all …]
Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
[all …]
Dt2081qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 phy-handle = <&phy_sgmii_s7_1c>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_s7_1d>;
64 phy-connection-type = "sgmii";
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
/Linux-v6.1/arch/arm64/boot/dts/amlogic/
Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]
/Linux-v6.1/arch/arm/boot/dts/
Dqcom-ipq8064-rb3011.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-ipq8064.dtsi"
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/leds/common.h>
7 model = "MikroTik RB3011UiAS-RM";
14 mdio-gpio0 = &mdio0;
15 mdio-gpio1 = &mdio1;
20 stdout-path = "serial0:115200n8";
28 mdio0: mdio-0 {
30 compatible = "virtual,mdio-gpio";
[all …]
Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
[all …]
Dgemini-ssi1328.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
24 mdio-gpio0 = &mdio0;
29 stdout-path = &uart0;
32 mdio0: mdio {
33 compatible = "virtual,mdio-gpio";
35 <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
36 #address-cells = <1>;
[all …]
Dls1021a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 /dts-v1/;
12 compatible = "fsl,ls1021a-qds", "fsl,ls1021a";
22 sys_mclk: clock-mclk {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <24576000>;
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
[all …]
/Linux-v6.1/drivers/net/mdio/
Dmdio-mux-meson-g12a.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
12 #include <linux/mdio-mux.h>
26 #define PLL_MUX_NUM_PARENT 2
38 #define PHY_CNTL1_ST_MODE GENMASK(2, 0)
76 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()
86 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
90 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
94 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
101 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()
[all …]

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